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feat(intc): DSS INTC driver implementation and host unit tests #108

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hoogv merged 1 commit from feat/107-dss-intc-driver into dev

2026-07-23 18:45:23 +00:00

hoogv commented

2026-07-23 18:45:02 +00:00

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Description

Adds hal/dss/intc/hal_dss_intc.c/.h — the C674x DSP's Interrupt Selector driver. The C674x's interrupt architecture is fundamentally two separate mechanisms, unlike the MSS/R4F's single VIM: (1) the memory-mapped, host-testable Interrupt Selector this driver covers — hal_dss_intc_map_event_to_vector()/_get_event_for_vector() program/read back which of up to 128 SoC-wide system events lands on which CPU interrupt (INT4-INT15, via INTMUX1-3), hal_dss_intc_event_flag()/_set()/_clear()/_mask()/_unmask() operate on individual event flags, hal_dss_intc_check_dropped_event()/_clear_dropped_event() decode INTXSTAT drop detection; and (2) the CPU's own non-memory-mapped interrupt state (IER/ICR/ISTP/CSR.GIE), covered by hal_dss_intc_enable_vector()/_disable_vector()/_clear_vector_pending()/_set_vector_table()/_enable_global_interrupts()/_disable_global_interrupts(), all cl6x-only (TI-compiler __cregister extensions, guarded #if defined(_TMS320C6X)) and absent entirely from the host-test build — there is no fake-register shim possible for non-addressable compiler registers.

Carries forward an empirically-confirmed open hardware risk from this project's prior investigation, documented in the header's top-of-file comment: even with a fully TRM/SPRUFK5A-correct register sequence, a bare hand-rolled ISR (no SYS/BIOS-style dispatcher) has been observed to occasionally mis-dispatch on real AWR6843 silicon (landing in INT15's vector instead of the intended one) — root cause unresolved, flagged as a known, open risk rather than a solved problem.

Why

Continues the DSS-side driver batch (Mailbox, EDMA, VIM, DSS ADCBUF already landed) with system-event-to-CPU-vector routing for the DSS core.

Closes #107

Type of Change

New feature

Impact Assessment

Functional impact: None — self-contained addition alongside the already-landed Mailbox/EDMA/VIM/DSS-ADCBUF drivers.
Regulatory impact: None.
QMS impact: None.
Risk impact: No new risk beyond the documented, pre-existing, unresolved hand-rolled-ISR dispatch-reliability caveat this driver's header carries forward from prior hardware investigation — existing risk coverage otherwise sufficient.

Testing

CI pipeline passes (compile, unit tests, integration tests, static analysis)
Manually tested: built and ran testing/dss/intc/test_dss_intc_functional locally (7 test cases, 41 assertions, all passing) alongside the full existing ctest suite (373/373 passing, no regressions); ran a full MISRA C:2025 pass (0 unsuppressed findings, -DENABLE_DSS_INTC_MODULE added); reformatted and re-verified against the exact clang-format 18.1.3 the CI runner uses; sanity-checked by widening hal_dss_intc_map_event_to_vector()'s packed-field mask from 0x7FUL to 0xFFUL (clobbering the reserved bit), confirming the test suite fails (1 assertion), then reverting.
No regressions observed in related areas

PR Size

XL (> 300 lines) — must split unless exemption declared

Size justification / exemption (if L or XL):

663 raw lines across 6 files, all hand-reviewed (no mechanically-generated content). Not split further — the driver (hal_dss_intc.c/.h, 485 lines, most of it the .h's doc comments and the two-mechanism hardware-caveat explanation) and its Catch2 spec (test_dss_intc.c, 169 lines) don't decompose into independently-reviewable sub-PRs, same rationale as every prior driver PR in this project. The remaining files are small CMake/MISRA wiring diffs, also not independently reviewable apart from the driver they enable.

Checklist

Commit messages follow type(scope): description convention with Relates to #<issue> footer
PR template filled in completely
No unverified external binaries introduced (see QMS-GITFLOW-001 Binary Security section)
All commits leave the codebase in a compilable, passing-tests state (Commit Integrity Rule)

Summary

hal/dss/intc/hal_dss_intc.c/.h: DSS INTC (C674x Interrupt Selector) driver — memory-mapped event-to-vector routing, event flag/set/clear/mask, dropped-event detection; cl6x-only CPU cregister functions guarded #if defined(_TMS320C6X)
testing/dss/intc/test_dss_intc.c (+ CMakeLists.txt, target named test_dss_intc_functional to avoid a collision with ti_hal_comparison/test_dss_intc.c): Catch2 functional test suite for the memory-mapped API
testing/CMakeLists.txt: add_subdirectory(dss/intc) and ENABLE_DSS_INTC_MODULE in the shared hw_fakes compile definitions
tools/misra/run_misra.sh: -DENABLE_DSS_INTC_MODULE added

## Description Adds `hal/dss/intc/hal_dss_intc.c`/`.h` — the C674x DSP's Interrupt Selector driver. The C674x's interrupt architecture is fundamentally two separate mechanisms, unlike the MSS/R4F's single VIM: (1) the memory-mapped, host-testable Interrupt Selector this driver covers — `hal_dss_intc_map_event_to_vector()`/`_get_event_for_vector()` program/read back which of up to 128 SoC-wide system events lands on which CPU interrupt (INT4-INT15, via `INTMUX1-3`), `hal_dss_intc_event_flag()`/`_set()`/`_clear()`/`_mask()`/`_unmask()` operate on individual event flags, `hal_dss_intc_check_dropped_event()`/`_clear_dropped_event()` decode `INTXSTAT` drop detection; and (2) the CPU's own non-memory-mapped interrupt state (IER/ICR/ISTP/CSR.GIE), covered by `hal_dss_intc_enable_vector()`/`_disable_vector()`/`_clear_vector_pending()`/`_set_vector_table()`/`_enable_global_interrupts()`/`_disable_global_interrupts()`, all `cl6x`-only (TI-compiler `__cregister` extensions, guarded `#if defined(_TMS320C6X)`) and absent entirely from the host-test build — there is no fake-register shim possible for non-addressable compiler registers. Carries forward an empirically-confirmed open hardware risk from this project's prior investigation, documented in the header's top-of-file comment: even with a fully TRM/SPRUFK5A-correct register sequence, a bare hand-rolled ISR (no SYS/BIOS-style dispatcher) has been observed to occasionally mis-dispatch on real AWR6843 silicon (landing in INT15's vector instead of the intended one) — root cause unresolved, flagged as a known, open risk rather than a solved problem. ## Why Continues the DSS-side driver batch (Mailbox, EDMA, VIM, DSS ADCBUF already landed) with system-event-to-CPU-vector routing for the DSS core. ## Related Issue Closes #107 ## Type of Change - [x] New feature ## Impact Assessment - **Functional impact:** None — self-contained addition alongside the already-landed Mailbox/EDMA/VIM/DSS-ADCBUF drivers. - **Regulatory impact:** None. - **QMS impact:** None. - **Risk impact:** No new risk beyond the documented, pre-existing, unresolved hand-rolled-ISR dispatch-reliability caveat this driver's header carries forward from prior hardware investigation — existing risk coverage otherwise sufficient. ## Testing - [x] CI pipeline passes (compile, unit tests, integration tests, static analysis) - [x] Manually tested: built and ran `testing/dss/intc/test_dss_intc_functional` locally (7 test cases, 41 assertions, all passing) alongside the full existing `ctest` suite (373/373 passing, no regressions); ran a full MISRA C:2025 pass (0 unsuppressed findings, `-DENABLE_DSS_INTC_MODULE` added); reformatted and re-verified against the exact clang-format 18.1.3 the CI runner uses; sanity-checked by widening `hal_dss_intc_map_event_to_vector()`'s packed-field mask from `0x7FUL` to `0xFFUL` (clobbering the reserved bit), confirming the test suite fails (1 assertion), then reverting. - [x] No regressions observed in related areas ## PR Size - [x] XL (> 300 lines) — must split unless exemption declared **Size justification / exemption (if L or XL):** 663 raw lines across 6 files, all hand-reviewed (no mechanically-generated content). Not split further — the driver (`hal_dss_intc.c`/`.h`, 485 lines, most of it the `.h`'s doc comments and the two-mechanism hardware-caveat explanation) and its Catch2 spec (`test_dss_intc.c`, 169 lines) don't decompose into independently-reviewable sub-PRs, same rationale as every prior driver PR in this project. The remaining files are small CMake/MISRA wiring diffs, also not independently reviewable apart from the driver they enable. ## Checklist - [x] Commit messages follow `type(scope): description` convention with `Relates to #<issue>` footer - [x] PR template filled in completely - [x] No unverified external binaries introduced (see QMS-GITFLOW-001 Binary Security section) - [x] All commits leave the codebase in a compilable, passing-tests state (Commit Integrity Rule) ## Summary - `hal/dss/intc/hal_dss_intc.c`/`.h`: DSS INTC (C674x Interrupt Selector) driver — memory-mapped event-to-vector routing, event flag/set/clear/mask, dropped-event detection; cl6x-only CPU cregister functions guarded `#if defined(_TMS320C6X)` - `testing/dss/intc/test_dss_intc.c` (+ `CMakeLists.txt`, target named `test_dss_intc_functional` to avoid a collision with `ti_hal_comparison/test_dss_intc.c`): Catch2 functional test suite for the memory-mapped API - `testing/CMakeLists.txt`: `add_subdirectory(dss/intc)` and `ENABLE_DSS_INTC_MODULE` in the shared `hw_fakes` compile definitions - `tools/misra/run_misra.sh`: `-DENABLE_DSS_INTC_MODULE` added

hoogv added 1 commit

2026-07-23 18:45:02 +00:00

feat(intc): DSS INTC driver implementation and host unit tests

lint / clang-format (pull_request) Successful in 11s

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tests / host-tests (pull_request) Successful in 44s

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57963fa472

Adds the C674x DSP's Interrupt Selector driver: memory-mapped
event-to-vector routing (INTMUX), per-event flag/set/clear/mask
(EVTFLAG/EVTSET/EVTCLR/EVTMASK), and dropped-event detection
(INTXSTAT/INTXCLR), all host-testable. The CPU's own cregister
interrupt state (IER/ICR/ISTP/CSR.GIE) is cl6x-only, guarded
#if defined(_TMS320C6X), and out of scope for host tests since
there's no fake-register shim possible for non-addressable
compiler registers.

Closes #107

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>

hoogv merged commit 57963fa472 into dev

2026-07-23 18:45:23 +00:00

hoogv added this to the Revision V1.0 Launch milestone

2026-07-23 18:45:28 +00:00

hoogv added this to the Development project

2026-07-23 18:45:30 +00:00

hoogv self-assigned this

2026-07-23 18:45:31 +00:00

hoogv added the

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