opendutchsolutions.public/hal_awr6843

Fork 0

feat(cache): DSS Cache driver implementation and host unit tests #110

Merged

hoogv merged 1 commit from feat/109-dss-cache-driver into dev

2026-07-23 18:54:08 +00:00

hoogv commented

2026-07-23 18:53:18 +00:00

Owner

Description

Adds hal/dss/cache/hal_dss_cache.c/.h — a deliberately narrow driver for the C674x DSP's L1P/L1D/L2 cache module: read-only access to L1PCFG.L1PMODE/L1DCFG.L1DMODE/L2CFG.L2MODE (hal_dss_cache_l1p_mode()/_l1d_mode()/_l2_mode()), the seven documented self-clearing global coherence-operation triggers (hal_dss_cache_l1p_invalidate(), _l1d_invalidate(), _l1d_writeback(), _l1d_writeback_invalidate(), _l2_invalidate(), _l2_writeback(), _l2_writeback_invalidate() — each a bounded poll-for-completion, same #define-timeout pattern as hal_adcbuf.c's ECC-init poll), and bounds-checked indexed read/write of the 256-entry Memory Attribute Register array (hal_dss_cache_mar_read()/_mar_write()).

Flagged in its own top-of-file comment as the least-verified, lowest-confidence driver in this project so far: register layout is unusually well corroborated (SPRUFK5A, TI's auto-generated reg_dspicfg.h, and the Linux kernel's C64x+ cache device trees all agree on every address/reserved-gap), but this project has no source for the operational-sequencing guidance TI's separate Cache User's Guide (SPRUG82) would normally provide. The driver deliberately stays out of that territory — no cache-mode writes, no block/address-range coherence operations, no freeze-mode controls, and no invented multi-register "safe flush" sequence; composing these primitives is left entirely to the caller.

Why

Continues the DSS-side driver batch (Mailbox, EDMA, VIM, DSS ADCBUF, DSS INTC already landed).

Closes #109

Type of Change

New feature

Impact Assessment

Functional impact: None — self-contained addition alongside the already-landed Mailbox/EDMA/VIM/DSS-ADCBUF/DSS-INTC drivers.
Regulatory impact: None.
QMS impact: None.
Risk impact: No new risk — this driver explicitly narrows its own scope to stay within what SPRUFK5A's register reference supports, and documents rather than papers over the operational-sequencing gap left by the absence of TI's Cache User's Guide.

Testing

CI pipeline passes (compile, unit tests, integration tests, static analysis)
Manually tested: built and ran testing/dss/cache/test_dss_cache_functional locally (4 test cases, 29 assertions, all passing) alongside the full existing ctest suite (377/377 passing, no regressions); ran a full MISRA C:2025 pass (0 unsuppressed findings, -DENABLE_DSS_CACHE_MODULE added); reformatted and re-verified against the exact clang-format 18.1.3 the CI runner uses; sanity-checked by swapping hal_dss_cache_l2_invalidate()'s target register from L2INV to L2WB, confirming the test suite fails (1 assertion), then reverting.
No regressions observed in related areas

PR Size

XL (> 300 lines) — must split unless exemption declared

Size justification / exemption (if L or XL):

611 raw lines across 6 files, all hand-reviewed (no mechanically-generated content). Not split further — the driver (hal_dss_cache.c/.h, 414 lines, most of it the .h's doc comments and the extensive confidence-boundary explanation) and its Catch2 spec (test_dss_cache.c, 188 lines) don't decompose into independently-reviewable sub-PRs, same rationale as every prior driver PR in this project. The remaining files are small CMake/MISRA wiring diffs, also not independently reviewable apart from the driver they enable.

Checklist

Commit messages follow type(scope): description convention with Relates to #<issue> footer
PR template filled in completely
No unverified external binaries introduced (see QMS-GITFLOW-001 Binary Security section)
All commits leave the codebase in a compilable, passing-tests state (Commit Integrity Rule)

Summary

hal/dss/cache/hal_dss_cache.c/.h: DSS Cache driver — read-only cache-mode queries, 7 global coherence-operation triggers, bounds-checked MAR array access
testing/dss/cache/test_dss_cache.c (+ CMakeLists.txt, target named test_dss_cache_functional to avoid a collision with ti_hal_comparison/test_dss_cache.c): Catch2 functional test suite
testing/CMakeLists.txt: add_subdirectory(dss/cache) and ENABLE_DSS_CACHE_MODULE in the shared hw_fakes compile definitions
tools/misra/run_misra.sh: -DENABLE_DSS_CACHE_MODULE added

## Description Adds `hal/dss/cache/hal_dss_cache.c`/`.h` — a deliberately narrow driver for the C674x DSP's L1P/L1D/L2 cache module: read-only access to `L1PCFG.L1PMODE`/`L1DCFG.L1DMODE`/`L2CFG.L2MODE` (`hal_dss_cache_l1p_mode()`/`_l1d_mode()`/`_l2_mode()`), the seven documented self-clearing global coherence-operation triggers (`hal_dss_cache_l1p_invalidate()`, `_l1d_invalidate()`, `_l1d_writeback()`, `_l1d_writeback_invalidate()`, `_l2_invalidate()`, `_l2_writeback()`, `_l2_writeback_invalidate()` — each a bounded poll-for-completion, same `#define`-timeout pattern as `hal_adcbuf.c`'s ECC-init poll), and bounds-checked indexed read/write of the 256-entry Memory Attribute Register array (`hal_dss_cache_mar_read()`/`_mar_write()`). Flagged in its own top-of-file comment as **the least-verified, lowest-confidence driver in this project so far**: register *layout* is unusually well corroborated (SPRUFK5A, TI's auto-generated `reg_dspicfg.h`, and the Linux kernel's C64x+ cache device trees all agree on every address/reserved-gap), but this project has no source for the operational-sequencing guidance TI's separate Cache User's Guide (SPRUG82) would normally provide. The driver deliberately stays out of that territory — no cache-mode *writes*, no block/address-range coherence operations, no freeze-mode controls, and no invented multi-register "safe flush" sequence; composing these primitives is left entirely to the caller. ## Why Continues the DSS-side driver batch (Mailbox, EDMA, VIM, DSS ADCBUF, DSS INTC already landed). ## Related Issue Closes #109 ## Type of Change - [x] New feature ## Impact Assessment - **Functional impact:** None — self-contained addition alongside the already-landed Mailbox/EDMA/VIM/DSS-ADCBUF/DSS-INTC drivers. - **Regulatory impact:** None. - **QMS impact:** None. - **Risk impact:** No new risk — this driver explicitly narrows its own scope to stay within what SPRUFK5A's register reference supports, and documents rather than papers over the operational-sequencing gap left by the absence of TI's Cache User's Guide. ## Testing - [x] CI pipeline passes (compile, unit tests, integration tests, static analysis) - [x] Manually tested: built and ran `testing/dss/cache/test_dss_cache_functional` locally (4 test cases, 29 assertions, all passing) alongside the full existing `ctest` suite (377/377 passing, no regressions); ran a full MISRA C:2025 pass (0 unsuppressed findings, `-DENABLE_DSS_CACHE_MODULE` added); reformatted and re-verified against the exact clang-format 18.1.3 the CI runner uses; sanity-checked by swapping `hal_dss_cache_l2_invalidate()`'s target register from `L2INV` to `L2WB`, confirming the test suite fails (1 assertion), then reverting. - [x] No regressions observed in related areas ## PR Size - [x] XL (> 300 lines) — must split unless exemption declared **Size justification / exemption (if L or XL):** 611 raw lines across 6 files, all hand-reviewed (no mechanically-generated content). Not split further — the driver (`hal_dss_cache.c`/`.h`, 414 lines, most of it the `.h`'s doc comments and the extensive confidence-boundary explanation) and its Catch2 spec (`test_dss_cache.c`, 188 lines) don't decompose into independently-reviewable sub-PRs, same rationale as every prior driver PR in this project. The remaining files are small CMake/MISRA wiring diffs, also not independently reviewable apart from the driver they enable. ## Checklist - [x] Commit messages follow `type(scope): description` convention with `Relates to #<issue>` footer - [x] PR template filled in completely - [x] No unverified external binaries introduced (see QMS-GITFLOW-001 Binary Security section) - [x] All commits leave the codebase in a compilable, passing-tests state (Commit Integrity Rule) ## Summary - `hal/dss/cache/hal_dss_cache.c`/`.h`: DSS Cache driver — read-only cache-mode queries, 7 global coherence-operation triggers, bounds-checked MAR array access - `testing/dss/cache/test_dss_cache.c` (+ `CMakeLists.txt`, target named `test_dss_cache_functional` to avoid a collision with `ti_hal_comparison/test_dss_cache.c`): Catch2 functional test suite - `testing/CMakeLists.txt`: `add_subdirectory(dss/cache)` and `ENABLE_DSS_CACHE_MODULE` in the shared `hw_fakes` compile definitions - `tools/misra/run_misra.sh`: `-DENABLE_DSS_CACHE_MODULE` added

hoogv added 1 commit

2026-07-23 18:53:18 +00:00

feat(cache): DSS Cache driver implementation and host unit tests

lint / clang-format (pull_request) Successful in 11s

Details

tests / host-tests (pull_request) Successful in 44s

Details

lint / misra (pull_request) Successful in 1m3s

Details

lint / clang-format (push) Successful in 11s

Details

tests / host-tests (push) Successful in 44s

Details

lint / misra (push) Successful in 1m0s

Details

ac35a97a76

Adds a deliberately narrow driver for the C674x DSP's L1P/L1D/L2
cache module: read-only cache-mode queries, the seven documented
self-clearing global coherence-operation triggers (invalidate/
writeback/writeback-invalidate at L1P/L1D/L2), and bounds-checked
indexed access to the 256-entry MAR array. Flagged in its own
header comment as this project's least-verified driver so far:
register layout is well corroborated across three independent
sources, but there is no source for TI's Cache User's Guide-level
operational sequencing guidance, so this driver deliberately stays
out of cache-mode writes, block/range operations, and any invented
multi-register "safe flush" sequence.

Closes #109

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>

hoogv added this to the Revision V1.0 Launch milestone

2026-07-23 18:53:56 +00:00

hoogv added this to the Development project

2026-07-23 18:53:58 +00:00

hoogv self-assigned this

2026-07-23 18:54:01 +00:00

hoogv merged commit ac35a97a76 into dev

2026-07-23 18:54:08 +00:00

hoogv added the

Rows
Columns