feat(dss-hwa): DSS HWA driver implementation and host unit tests #112

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hoogv merged 1 commit from feat/111-dss-hwa-driver into dev 2026-07-23 18:59:54 +00:00
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Description

Adds hal/dss/hwa/hal_dss_hwa.c/.h — the DSS-side counterpart of the already-landed MSS HWA driver (#95/#96). Same physical Hardware Accelerator, dual-mapped at DSS-visible addresses (DSS_HWA1/DSS_HWA1_PARAM) instead of MSS's. Named hal_dss_hwa_*() rather than hal_hwa_*() to avoid collision should both ever be linked into the same firmware image.

Provides hal_dss_hwa_init() (TI mmWave SDK hwa.c-sourced bring-up sequence: disable, pulse ACCRESET, ungate clock, clear stale PARAMDONESTAT, zero all 16 param-RAM entries), hal_dss_hwa_load_param_set() (raw 32-byte param-set blob write — deliberately not a structured-field API, same rationale as the MSS driver), hal_dss_hwa_trigger() (single contiguous PARAMSTART..PARAMSTOP range, NLOOPS = 0), and hal_dss_hwa_is_done() (poll-only HWACCREG4.PARAMDONESTAT, no ISR path — DSS-local PARAM_DONE interrupts exist but are out of scope here, matching the MSS driver's polling-only shape).

Carries forward the same documented scope limits as the MSS driver: no real FFT/CFAR/log-magnitude/compression correctness validation, no individual PARAMn_x field API, no DMA-triggered param-sets or looped execution.

Why

Continues the DSS-side driver batch (Mailbox, EDMA, VIM, DSS ADCBUF, DSS INTC, DSS Cache already landed) with HWA parity for the DSS core.

Closes #111

Type of Change

  • New feature

Impact Assessment

  • Functional impact: None — self-contained addition alongside the already-landed Mailbox/EDMA/VIM/DSS-ADCBUF/DSS-INTC/DSS-Cache drivers.
  • Regulatory impact: None.
  • QMS impact: None.
  • Risk impact: No new risk — same documented scope limits as the already-landed MSS HWA driver.

Testing

  • CI pipeline passes (compile, unit tests, integration tests, static analysis)
  • Manually tested: built and ran testing/dss/hwa/test_dss_hwa locally (10 test cases, 77 assertions, all passing) alongside the full existing ctest suite (387/387 passing, no regressions); ran a full MISRA C:2025 pass (0 unsuppressed findings, -DENABLE_DSS_HWA_MODULE added); reformatted and re-verified against the exact clang-format 18.1.3 the CI runner uses; sanity-checked by dropping the + 1U from hwa_range_mask()'s inclusive-range bit count, confirming the test suite fails (4 assertions across 3 test cases), then reverting.
  • No regressions observed in related areas

PR Size

  • XL (> 300 lines) — must split unless exemption declared

Size justification / exemption (if L or XL):

642 raw lines across 6 files, all hand-reviewed (no mechanically-generated content). Not split further — the driver (hal_dss_hwa.c/.h, 396 lines) and its Catch2 spec (test_dss_hwa.c, 241 lines) don't decompose into independently-reviewable sub-PRs, same rationale as every prior driver PR in this project. The remaining files are small CMake/MISRA wiring diffs, also not independently reviewable apart from the driver they enable.

Checklist

  • Commit messages follow type(scope): description convention with Relates to #<issue> footer
  • PR template filled in completely
  • No unverified external binaries introduced (see QMS-GITFLOW-001 Binary Security section)
  • All commits leave the codebase in a compilable, passing-tests state (Commit Integrity Rule)

Summary

  • hal/dss/hwa/hal_dss_hwa.c/.h: DSS HWA driver — init/bring-up, raw param-set load, single-range trigger, poll-only completion check
  • testing/dss/hwa/test_dss_hwa.c (+ CMakeLists.txt): Catch2 functional test suite. No naming collision with ti_hal_comparison (that suite's HWA test is test_hwa, not test_dss_hwa).
  • testing/CMakeLists.txt: add_subdirectory(dss/hwa) and ENABLE_DSS_HWA_MODULE in the shared hw_fakes compile definitions
  • tools/misra/run_misra.sh: -DENABLE_DSS_HWA_MODULE added
## Description Adds `hal/dss/hwa/hal_dss_hwa.c`/`.h` — the DSS-side counterpart of the already-landed MSS HWA driver (#95/#96). Same physical Hardware Accelerator, dual-mapped at DSS-visible addresses (`DSS_HWA1`/`DSS_HWA1_PARAM`) instead of MSS's. Named `hal_dss_hwa_*()` rather than `hal_hwa_*()` to avoid collision should both ever be linked into the same firmware image. Provides `hal_dss_hwa_init()` (TI mmWave SDK `hwa.c`-sourced bring-up sequence: disable, pulse `ACCRESET`, ungate clock, clear stale `PARAMDONESTAT`, zero all 16 param-RAM entries), `hal_dss_hwa_load_param_set()` (raw 32-byte param-set blob write — deliberately not a structured-field API, same rationale as the MSS driver), `hal_dss_hwa_trigger()` (single contiguous `PARAMSTART..PARAMSTOP` range, `NLOOPS = 0`), and `hal_dss_hwa_is_done()` (poll-only `HWACCREG4.PARAMDONESTAT`, no ISR path — DSS-local `PARAM_DONE` interrupts exist but are out of scope here, matching the MSS driver's polling-only shape). Carries forward the same documented scope limits as the MSS driver: no real FFT/CFAR/log-magnitude/compression correctness validation, no individual `PARAMn_x` field API, no DMA-triggered param-sets or looped execution. ## Why Continues the DSS-side driver batch (Mailbox, EDMA, VIM, DSS ADCBUF, DSS INTC, DSS Cache already landed) with HWA parity for the DSS core. ## Related Issue Closes #111 ## Type of Change - [x] New feature ## Impact Assessment - **Functional impact:** None — self-contained addition alongside the already-landed Mailbox/EDMA/VIM/DSS-ADCBUF/DSS-INTC/DSS-Cache drivers. - **Regulatory impact:** None. - **QMS impact:** None. - **Risk impact:** No new risk — same documented scope limits as the already-landed MSS HWA driver. ## Testing - [x] CI pipeline passes (compile, unit tests, integration tests, static analysis) - [x] Manually tested: built and ran `testing/dss/hwa/test_dss_hwa` locally (10 test cases, 77 assertions, all passing) alongside the full existing `ctest` suite (387/387 passing, no regressions); ran a full MISRA C:2025 pass (0 unsuppressed findings, `-DENABLE_DSS_HWA_MODULE` added); reformatted and re-verified against the exact clang-format 18.1.3 the CI runner uses; sanity-checked by dropping the `+ 1U` from `hwa_range_mask()`'s inclusive-range bit count, confirming the test suite fails (4 assertions across 3 test cases), then reverting. - [x] No regressions observed in related areas ## PR Size - [x] XL (> 300 lines) — must split unless exemption declared **Size justification / exemption (if L or XL):** 642 raw lines across 6 files, all hand-reviewed (no mechanically-generated content). Not split further — the driver (`hal_dss_hwa.c`/`.h`, 396 lines) and its Catch2 spec (`test_dss_hwa.c`, 241 lines) don't decompose into independently-reviewable sub-PRs, same rationale as every prior driver PR in this project. The remaining files are small CMake/MISRA wiring diffs, also not independently reviewable apart from the driver they enable. ## Checklist - [x] Commit messages follow `type(scope): description` convention with `Relates to #<issue>` footer - [x] PR template filled in completely - [x] No unverified external binaries introduced (see QMS-GITFLOW-001 Binary Security section) - [x] All commits leave the codebase in a compilable, passing-tests state (Commit Integrity Rule) ## Summary - `hal/dss/hwa/hal_dss_hwa.c`/`.h`: DSS HWA driver — init/bring-up, raw param-set load, single-range trigger, poll-only completion check - `testing/dss/hwa/test_dss_hwa.c` (+ `CMakeLists.txt`): Catch2 functional test suite. No naming collision with `ti_hal_comparison` (that suite's HWA test is `test_hwa`, not `test_dss_hwa`). - `testing/CMakeLists.txt`: `add_subdirectory(dss/hwa)` and `ENABLE_DSS_HWA_MODULE` in the shared `hw_fakes` compile definitions - `tools/misra/run_misra.sh`: `-DENABLE_DSS_HWA_MODULE` added
feat(dss-hwa): DSS HWA driver implementation and host unit tests
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e8debd7605
Adds the DSS-side counterpart of the already-landed MSS HWA driver:
same physical Hardware Accelerator, dual-mapped at DSS_HWA1/
DSS_HWA1_PARAM instead of MSS's addresses. Provides init (TI mmWave
SDK-sourced bring-up sequence), raw param-set blob load, single
contiguous-range trigger, and poll-only completion check -- no ISR
path, matching the MSS driver's scope exactly.

Closes #111

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
hoogv added this to the Development project 2026-07-23 18:59:49 +00:00
hoogv self-assigned this 2026-07-23 18:59:50 +00:00
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