feat(rti): MSS RTI driver implementation and host unit tests #117

Merged

hoogv merged 1 commit from feat/116-mss-rti-driver into dev

2026-07-23 19:52:53 +00:00

hoogv commented

2026-07-23 19:51:07 +00:00

Owner

Description

Adds hal/mss/rti/hal_rti.c/.h — driver for the two MSS-side RTI (Real-Time Interrupt) timer instances, MSS_RTIA and MSS_RTIB (TRM Table 4-2). MSS_RTIA is a plain free-running timer; MSS_RTIB is the same Hercules RTI IP block additionally wired as the device's Digital Watchdog Timer. Mirrors the already-landed DSS RTI driver's (#113/#114) scope: counter block 0 / compare channel 0 only — no watchdog-mode registers, no counter block 1 / compare channels 1-3, no external NTU timebase/capture, no DMA-request wiring.

Unlike DSS, MSS interrupts route through the VIM — this driver adds a real VIM-dispatched raw handler, RTI_COMPARE0_IRQHandler() (VIM channel 2, RTI_COMPARE0_IRQn), acknowledging RTIINTFLAG.INT0 and forwarding to a weak, application-overridable hal_rti_irq_handler() hook, plus a new case in hal_vim.c's dispatch switch. This handler is scoped to MSS_RTIA only — MSS_RTIB's compare-0 interrupt routes through the differently-numbered WDT_REQ0_IRQn (channel 10) instead, per its watchdog wiring.

Also adds fake_mss_rtia/fake_mss_rtib host-test register shims (the RTIA/RTIB typed macros had no fake backing before this PR).

Caller-facing safety note, documented in the header: because MSS_RTIB is the device's live watchdog block, calling this driver's generic counter-block-0 functions against HAL_RTI_B shares hardware with whatever watchdog configuration is (or isn't) active on that instance — this driver does not itself arm, disarm, or otherwise know about the watchdog.

Why

Completes MSS/DSS RTI driver parity, and is a direct prerequisite for the barebones MSS example project currently being scaffolded, which needs a real periodic interrupt source to demonstrate the VIM dispatch chain.

Closes #116

Type of Change

New feature

Impact Assessment

Functional impact: None — self-contained addition; completes MSS/DSS RTI driver parity.
Regulatory impact: None.
QMS impact: None.
Risk impact: The MSS_RTIB-is-also-the-watchdog caveat is a genuine, documented risk boundary (not a defect) — this driver deliberately does not touch watchdog-mode registers and calls out the shared-hardware hazard explicitly.

Testing

CI pipeline passes (compile, unit tests, integration tests, static analysis)
Manually tested: built and ran testing/mss/unit/hal_functionality/test_rti_functional locally (6 test cases, 67 assertions, all passing) alongside the full existing ctest suite (398/398 passing, no regressions), plus confirmed test_vim_functional/test_vim_dispatch still link and pass with hal_rti.c; ran a full MISRA C:2025 pass (0 unsuppressed findings, -DENABLE_RTI_MODULE added); reformatted and re-verified against the exact clang-format 18.1.3 the CI runner uses. Sanity-checked by swapping RTI_COMPARE0_IRQHandler()'s target instance from HAL_RTI_A to HAL_RTI_B — the first version of the test suite didn't catch this (it only asserted RTIA's flag state, which a write-1-to-clear fake can't tell apart from "written again"), so the test was fixed to also assert RTIB stays untouched before re-running the sanity check, which then correctly failed (1 assertion) and was reverted.
No regressions observed in related areas

PR Size

XL (> 300 lines) — must split unless exemption declared

Size justification / exemption (if L or XL):

669 raw lines across 13 files, all hand-reviewed (no mechanically-generated content). Not split further — the driver (hal_rti.c/.h, 376 lines) and its Catch2 spec (test_rti.c, 253 lines) don't decompose into independently-reviewable sub-PRs, same rationale as every prior driver PR in this project. The remaining files are small CMake/Kconfig/MISRA/VIM-dispatch wiring diffs, also not independently reviewable apart from the driver they enable.

Checklist

Commit messages follow type(scope): description convention with Relates to #<issue> footer
PR template filled in completely
No unverified external binaries introduced (see QMS-GITFLOW-001 Binary Security section)
All commits leave the codebase in a compilable, passing-tests state (Commit Integrity Rule)

Summary

hal/mss/rti/hal_rti.c/.h: MSS RTI driver — init/bring-up, periodic-rate configuration, start/stop, interrupt-flag clear, RTI_COMPARE0_IRQHandler() for both RTIA/RTIB instances
hal/mss/vim/hal_vim.c: new RTI_COMPARE0_IRQn dispatch case
testing/mss/unit/hal_functionality/test_rti.c (+ CMakeLists.txt, target named test_rti_functional to avoid a collision with ti_hal_comparison/test_rti.c): Catch2 functional test suite
testing/support/fakes/registers/awr.h / hw_fakes.c: new fake_mss_rtia/fake_mss_rtib register shims
zephyr/Kconfig / zephyr/CMakeLists.txt / hal/util/hal_config_mss.h / template/hal_config_mss_template.h: HAL_AWR6843_RTI Kconfig option and ENABLE_RTI_MODULE bridge
tools/misra/run_misra.sh: -DENABLE_RTI_MODULE added

## Description Adds `hal/mss/rti/hal_rti.c`/`.h` — driver for the two MSS-side RTI (Real-Time Interrupt) timer instances, `MSS_RTIA` and `MSS_RTIB` (TRM Table 4-2). `MSS_RTIA` is a plain free-running timer; `MSS_RTIB` is the *same* Hercules RTI IP block additionally wired as the device's Digital Watchdog Timer. Mirrors the already-landed DSS RTI driver's (#113/#114) scope: counter block 0 / compare channel 0 only — no watchdog-mode registers, no counter block 1 / compare channels 1-3, no external NTU timebase/capture, no DMA-request wiring. Unlike DSS, MSS interrupts route through the VIM — this driver adds a real VIM-dispatched raw handler, `RTI_COMPARE0_IRQHandler()` (VIM channel 2, `RTI_COMPARE0_IRQn`), acknowledging `RTIINTFLAG.INT0` and forwarding to a weak, application-overridable `hal_rti_irq_handler()` hook, plus a new `case` in `hal_vim.c`'s dispatch switch. This handler is scoped to `MSS_RTIA` only — `MSS_RTIB`'s compare-0 interrupt routes through the differently-numbered `WDT_REQ0_IRQn` (channel 10) instead, per its watchdog wiring. Also adds `fake_mss_rtia`/`fake_mss_rtib` host-test register shims (the `RTIA`/`RTIB` typed macros had no fake backing before this PR). **Caller-facing safety note**, documented in the header: because `MSS_RTIB` is the device's live watchdog block, calling this driver's generic counter-block-0 functions against `HAL_RTI_B` shares hardware with whatever watchdog configuration is (or isn't) active on that instance — this driver does not itself arm, disarm, or otherwise know about the watchdog. ## Why Completes MSS/DSS RTI driver parity, and is a direct prerequisite for the barebones MSS example project currently being scaffolded, which needs a real periodic interrupt source to demonstrate the VIM dispatch chain. ## Related Issue Closes #116 ## Type of Change - [x] New feature ## Impact Assessment - **Functional impact:** None — self-contained addition; completes MSS/DSS RTI driver parity. - **Regulatory impact:** None. - **QMS impact:** None. - **Risk impact:** The `MSS_RTIB`-is-also-the-watchdog caveat is a genuine, documented risk boundary (not a defect) — this driver deliberately does not touch watchdog-mode registers and calls out the shared-hardware hazard explicitly. ## Testing - [x] CI pipeline passes (compile, unit tests, integration tests, static analysis) - [x] Manually tested: built and ran `testing/mss/unit/hal_functionality/test_rti_functional` locally (6 test cases, 67 assertions, all passing) alongside the full existing `ctest` suite (398/398 passing, no regressions), plus confirmed `test_vim_functional`/`test_vim_dispatch` still link and pass with `hal_rti.c`; ran a full MISRA C:2025 pass (0 unsuppressed findings, `-DENABLE_RTI_MODULE` added); reformatted and re-verified against the exact clang-format 18.1.3 the CI runner uses. Sanity-checked by swapping `RTI_COMPARE0_IRQHandler()`'s target instance from `HAL_RTI_A` to `HAL_RTI_B` — the *first* version of the test suite didn't catch this (it only asserted RTIA's flag state, which a write-1-to-clear fake can't tell apart from "written again"), so the test was fixed to also assert RTIB stays untouched before re-running the sanity check, which then correctly failed (1 assertion) and was reverted. - [x] No regressions observed in related areas ## PR Size - [x] XL (> 300 lines) — must split unless exemption declared **Size justification / exemption (if L or XL):** 669 raw lines across 13 files, all hand-reviewed (no mechanically-generated content). Not split further — the driver (`hal_rti.c`/`.h`, 376 lines) and its Catch2 spec (`test_rti.c`, 253 lines) don't decompose into independently-reviewable sub-PRs, same rationale as every prior driver PR in this project. The remaining files are small CMake/Kconfig/MISRA/VIM-dispatch wiring diffs, also not independently reviewable apart from the driver they enable. ## Checklist - [x] Commit messages follow `type(scope): description` convention with `Relates to #<issue>` footer - [x] PR template filled in completely - [x] No unverified external binaries introduced (see QMS-GITFLOW-001 Binary Security section) - [x] All commits leave the codebase in a compilable, passing-tests state (Commit Integrity Rule) ## Summary - `hal/mss/rti/hal_rti.c`/`.h`: MSS RTI driver — init/bring-up, periodic-rate configuration, start/stop, interrupt-flag clear, `RTI_COMPARE0_IRQHandler()` for both `RTIA`/`RTIB` instances - `hal/mss/vim/hal_vim.c`: new `RTI_COMPARE0_IRQn` dispatch case - `testing/mss/unit/hal_functionality/test_rti.c` (+ `CMakeLists.txt`, target named `test_rti_functional` to avoid a collision with `ti_hal_comparison/test_rti.c`): Catch2 functional test suite - `testing/support/fakes/registers/awr.h` / `hw_fakes.c`: new `fake_mss_rtia`/`fake_mss_rtib` register shims - `zephyr/Kconfig` / `zephyr/CMakeLists.txt` / `hal/util/hal_config_mss.h` / `template/hal_config_mss_template.h`: `HAL_AWR6843_RTI` Kconfig option and `ENABLE_RTI_MODULE` bridge - `tools/misra/run_misra.sh`: `-DENABLE_RTI_MODULE` added

hoogv added 1 commit

2026-07-23 19:51:07 +00:00

feat(rti): MSS RTI driver implementation and host unit tests

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e75e36fb20

Adds hal/mss/rti/hal_rti.c/.h for MSS_RTIA (free-running timer) and
MSS_RTIB (also the device's Digital Watchdog Timer) -- same
counter-block-0/compare-0 scope as the already-landed DSS RTI
driver. Unlike DSS, MSS interrupts route through the VIM: adds a
real RTI_COMPARE0_IRQHandler() (VIM channel 2, MSS_RTIA only --
MSS_RTIB's compare-0 routes through the separate WDT_REQ0_IRQn
channel per its watchdog wiring) wired into hal_vim.c's dispatch
switch, plus a weak hal_rti_irq_handler() notification hook. Adds
fake_mss_rtia/fake_mss_rtib host-test register shims (previously
unshimmed).

Closes #116

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>

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