fix(uart): force a reset edge and configure RX/TX pull state in hal_uart_init() #121

Merged

hoogv merged 1 commit from fix/120-uart-reset-pull into dev

2026-07-23 21:20:55 +00:00

hoogv commented

2026-07-23 21:20:37 +00:00

Owner

Closes #120.

Two gaps found diffing hal_uart_init() against a hardware-confirmed sibling driver while debugging a real UART failure report on a downstream consumer project:

SCIGCR0.RESET = 1 written directly, no 0 first -- a no-op if the module was already out of reset (plausible here: the SBL/flash tool uses this same SCI instance to receive the flashed image before jumping to the app).
SCIPIO7/SCIPIO8 (RX/TX pull disable/select) never written -- their reset values are pin/pad default-dependent per this project's own register header comments, not guaranteed.

Both fixed, matching the SDK reference driver (UartSci_open()) and a hardware-confirmed sibling project's own port of it.

Local verification:

ctest: 403/403 passing (clean full rebuild)
MISRA (tools/misra/run_misra.sh): 0 findings
clang-format --dry-run --Werror: clean

PR_Size/S

Closes #120. Two gaps found diffing `hal_uart_init()` against a hardware-confirmed sibling driver while debugging a real UART failure report on a downstream consumer project: 1. `SCIGCR0.RESET = 1` written directly, no `0` first -- a no-op if the module was already out of reset (plausible here: the SBL/flash tool uses this same SCI instance to receive the flashed image before jumping to the app). 2. `SCIPIO7`/`SCIPIO8` (RX/TX pull disable/select) never written -- their reset values are pin/pad default-dependent per this project's own register header comments, not guaranteed. Both fixed, matching the SDK reference driver (`UartSci_open()`) and a hardware-confirmed sibling project's own port of it. Local verification: - `ctest`: 403/403 passing (clean full rebuild) - MISRA (`tools/misra/run_misra.sh`): 0 findings - `clang-format --dry-run --Werror`: clean PR_Size/S

hoogv added 1 commit

2026-07-23 21:20:37 +00:00

fix(uart): force a reset edge and configure RX/TX pull state in hal_uart_init()

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46de50ac80

SCIGCR0.RESET was written directly to 1, a no-op if the module was
already out of reset -- concretely possible here, since the SBL/flash
tool uses this same SCI instance (the board's Application/User UART)
before jumping to the application. Now resets (0) then releases (1).

SCIPIO7/SCIPIO8 (RX/TX pull disable/select) were never written; their
reset values are pin/pad default-dependent per this project's own
register header comments, not guaranteed. Now explicitly pull-enabled
and pulled up on both pins, matching the SDK reference driver
(UartSci_open()).

Found by diffing against a hardware-confirmed sibling driver while
debugging a real-hardware UART failure report on a downstream consumer
project.

Fixes #120

hoogv merged commit 46de50ac80 into dev

2026-07-23 21:20:55 +00:00

hoogv added this to the Revision V1.0 Launch milestone

2026-07-23 21:21:00 +00:00

hoogv added this to the Development project

2026-07-23 21:21:01 +00:00

hoogv self-assigned this

2026-07-23 21:21:03 +00:00