feat(mpu): Cortex-R4F MPU (CP15) configuration driver #127

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hoogv merged 1 commit from feat/126-mpu-driver into dev

2026-07-23 23:16:14 +00:00

hoogv commented

2026-07-23 23:16:08 +00:00

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Closes #126.

New hal_mpu driver (ENABLE_MPU_MODULE): hal_mpu_config() disables the MPU, programs a 12-region table (peripheral space Strongly-Ordered -- the region that turned out to matter for real-hardware bring-up), then re-enables it. Not called automatically by hal_soc_init() -- a consumer opts in explicitly before hal_soc_init() if it touches write-ordering-sensitive peripheral sequences.

Values/order are a direct transliteration of a hardware-confirmed sibling project's own MPU bring-up, not independently re-derived (no TRM section available for this device's MPU region layout).

Wired through the standard ENABLE_MPU_MODULE/CONFIG_HAL_AWR6843_MPU config path (hal_config_mss.h, template/hal_config_mss_template.h, zephyr/Kconfig, zephyr/CMakeLists.txt, tools/misra/run_misra.sh, testing/CMakeLists.txt), matching every other driver's landing pattern.

Testability note: CP15 register access has no host-testable equivalent (see hal_mpu.h's top-of-file comment) -- hal_mpu_region_table (the data hal_mpu_config() applies) is exposed and host-tested instead; the CP15 primitives themselves are no-ops under MMWHAL_HOST_TEST_BUILD, same pattern mmwhal_types.h's own MMWHAL_DISABLE_IRQ()/MMWHAL_ENABLE_IRQ() already use. Sanity-checked: flipped region 5's memory type in the table, confirmed the new test caught it, reverted.

Local verification:

ctest: 411/411 passing (clean full rebuild, +8 new test cases/47 assertions)
MISRA (tools/misra/run_misra.sh): 0 findings (4 genuine misra-c2012-2.7 false positives from cppcheck not parsing GNU extended-asm operand lists -- same root cause as the existing misra-c2012-17.3 suppression -- addressed with targeted inline cppcheck-suppress comments rather than a blanket rule suppression)
clang-format --dry-run --Werror: clean

PR_Size/M

Closes #126. New `hal_mpu` driver (`ENABLE_MPU_MODULE`): `hal_mpu_config()` disables the MPU, programs a 12-region table (peripheral space Strongly-Ordered -- the region that turned out to matter for real-hardware bring-up), then re-enables it. Not called automatically by `hal_soc_init()` -- a consumer opts in explicitly before `hal_soc_init()` if it touches write-ordering-sensitive peripheral sequences. Values/order are a direct transliteration of a hardware-confirmed sibling project's own MPU bring-up, not independently re-derived (no TRM section available for this device's MPU region layout). Wired through the standard `ENABLE_MPU_MODULE`/`CONFIG_HAL_AWR6843_MPU` config path (`hal_config_mss.h`, `template/hal_config_mss_template.h`, `zephyr/Kconfig`, `zephyr/CMakeLists.txt`, `tools/misra/run_misra.sh`, `testing/CMakeLists.txt`), matching every other driver's landing pattern. Testability note: CP15 register access has no host-testable equivalent (see `hal_mpu.h`'s top-of-file comment) -- `hal_mpu_region_table` (the data `hal_mpu_config()` applies) is exposed and host-tested instead; the CP15 primitives themselves are no-ops under `MMWHAL_HOST_TEST_BUILD`, same pattern `mmwhal_types.h`'s own `MMWHAL_DISABLE_IRQ()`/`MMWHAL_ENABLE_IRQ()` already use. Sanity-checked: flipped region 5's memory type in the table, confirmed the new test caught it, reverted. Local verification: - `ctest`: 411/411 passing (clean full rebuild, +8 new test cases/47 assertions) - MISRA (`tools/misra/run_misra.sh`): 0 findings (4 genuine `misra-c2012-2.7` false positives from cppcheck not parsing GNU extended-asm operand lists -- same root cause as the existing `misra-c2012-17.3` suppression -- addressed with targeted inline `cppcheck-suppress` comments rather than a blanket rule suppression) - `clang-format --dry-run --Werror`: clean PR_Size/M

hoogv added 1 commit

2026-07-23 23:16:08 +00:00

feat(mpu): Cortex-R4F MPU (CP15) configuration driver

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a64fa90835

hal_soc_init() does no MPU configuration at all; this project's own
startup code disables it and leaves it disabled. Confirmed on real
AWR6843AOP hardware, via a controlled bisection, that this is NOT
equivalent to an explicit MPU region table for peripheral-register
sequences that depend on write ordering -- hal_pinmux_set_pin_function()'s
kick-unlock/write/kick-lock sequence needed peripheral space explicitly
marked Strongly-Ordered via an MPU region before it worked.

New hal_mpu driver (ENABLE_MPU_MODULE): hal_mpu_config() disables the
MPU, programs a 12-region table (peripheral space Strongly-Ordered,
the region that turned out to matter), re-enables it. Not called
automatically by hal_soc_init() -- a consumer opts in explicitly.
Values/order transliterated from a hardware-confirmed sibling
project's own MPU bring-up, not independently re-derived from a TRM
section (none available for this device's MPU region layout).

CP15 register access has no host-testable equivalent (unlike every
other driver in this HAL, which are memory-mapped peripherals); the
region table is exposed as plain data and is what's host-tested.

Fixes #126

hoogv merged commit a64fa90835 into dev

2026-07-23 23:16:14 +00:00

hoogv deleted branch feat/126-mpu-driver

2026-07-23 23:16:15 +00:00

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