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feat(soc): SOC driver implementation and host unit tests #96

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hoogv merged 1 commit from feat/95-soc-driver into dev

2026-07-23 15:36:34 +00:00

hoogv commented

2026-07-23 15:30:43 +00:00

Owner

Description

Adds hal/mss/soc/hal_soc.c/.h — SoC-level clock/reset bring-up (TOPRCM/RCM) and DSS power-domain control: hal_soc_bss_clock_init() (ungates BSS, bounded-poll APLL calibration), hal_soc_secure_firewall_open() (secure-part-only JTAG/logger firewall open), hal_soc_init() (convenience wrapper), hal_soc_dss_reset_release(), hal_soc_dss_unhalt()/hal_soc_dss_halt() (common bootloader-provided-power-on path), and hal_soc_dss_power_off()/hal_soc_dss_power_on() (full power-domain protocol, both correctly bounded-timeout). CP15 MPU region configuration is deliberately out of scope (documented in hal_soc.h's top-of-file comment). Self-contained — no cross-module dependency.

Why

Continues the driver-implementation phase started by GPIO (#75/#76), ESM (#77/#78), UART (#79/#80), I2C (#81/#82), SPI (#83/#84), ADCBUF (#85/#86), CBUFF (#87/#88), HWA (#89/#90), DMM (#91/#92), and EPWM (#93/#94).

Closes #95

Type of Change

New feature

Impact Assessment

Functional impact: None — self-contained addition alongside the already-landed GPIO/ESM/UART/I2C/SPI/ADCBUF/CBUFF/HWA/DMM/EPWM drivers.
Regulatory impact: None.
QMS impact: None.
Risk impact: No — existing risk coverage sufficient.

Testing

CI pipeline passes (compile, unit tests, integration tests, static analysis)
Manually tested: built and ran testing/mss/unit/hal_functionality/test_soc locally (16 test cases, 44 assertions, all passing) alongside the full existing ctest suite (309/309 passing, no regressions); ran a full MISRA C:2025 pass (0 unsuppressed findings, -DENABLE_SOC_MODULE added); reformatted and re-verified against the exact clang-format 18.1.3 the CI runner uses; sanity-checked by dropping the GEMGRSTN bit from hal_soc_dss_reset_release()'s DSSCTL write, confirming the test suite fails (1 assertion), then reverting.
No regressions observed in related areas

PR Size

XL (> 300 lines) — must split unless exemption declared

Size justification / exemption (if L or XL):

638 raw lines across 9 files, all hand-reviewed (no mechanically-generated content). Not split further — the driver (hal_soc.c/.h, 378 lines) and its comprehensive Catch2 spec (test_soc.c, 243 lines, covering the bounded-timeout poll paths, secure-vs-general-purpose-part branching, and power-off/power-on sequencing) don't decompose into independently-reviewable sub-PRs, same rationale as prior driver PRs (#78, #80, #82, #84, #86, #88, #90, #92, #94). The remaining files are small CMake/Kconfig/MISRA wiring diffs, also not independently reviewable apart from the driver they enable.

Checklist

Commit messages follow type(scope): description convention with Relates to #<issue> footer
PR template filled in completely
No unverified external binaries introduced (see QMS-GITFLOW-001 Binary Security section)
All commits leave the codebase in a compilable, passing-tests state (Commit Integrity Rule)

Summary

hal/mss/soc/hal_soc.c/.h: SoC-level bring-up driver (BSS clock init, secure firewall open, DSS reset/halt/unhalt/power-off/power-on) — CP15 MPU configuration out of scope, documented in the header's top-of-file comment
testing/mss/unit/hal_functionality/test_soc.c (+ CMakeLists.txt): Catch2 functional test suite. No naming collision — no ti_hal_comparison/test_soc.c exists (this is SoC-level TOPRCM/DSSREG bring-up logic, not a single register-defined peripheral).
zephyr/Kconfig / zephyr/CMakeLists.txt / hal/util/hal_config_mss.h: HAL_AWR6843_SOC Kconfig option and ENABLE_SOC_MODULE bridge, same pattern as every other landed driver
tools/misra/run_misra.sh: -DENABLE_SOC_MODULE added

## Description Adds `hal/mss/soc/hal_soc.c`/`.h` — SoC-level clock/reset bring-up (TOPRCM/RCM) and DSS power-domain control: `hal_soc_bss_clock_init()` (ungates BSS, bounded-poll APLL calibration), `hal_soc_secure_firewall_open()` (secure-part-only JTAG/logger firewall open), `hal_soc_init()` (convenience wrapper), `hal_soc_dss_reset_release()`, `hal_soc_dss_unhalt()`/`hal_soc_dss_halt()` (common bootloader-provided-power-on path), and `hal_soc_dss_power_off()`/`hal_soc_dss_power_on()` (full power-domain protocol, both correctly bounded-timeout). CP15 MPU region configuration is deliberately out of scope (documented in `hal_soc.h`'s top-of-file comment). Self-contained — no cross-module dependency. ## Why Continues the driver-implementation phase started by GPIO (#75/#76), ESM (#77/#78), UART (#79/#80), I2C (#81/#82), SPI (#83/#84), ADCBUF (#85/#86), CBUFF (#87/#88), HWA (#89/#90), DMM (#91/#92), and EPWM (#93/#94). ## Related Issue Closes #95 ## Type of Change - [x] New feature ## Impact Assessment - **Functional impact:** None — self-contained addition alongside the already-landed GPIO/ESM/UART/I2C/SPI/ADCBUF/CBUFF/HWA/DMM/EPWM drivers. - **Regulatory impact:** None. - **QMS impact:** None. - **Risk impact:** No — existing risk coverage sufficient. ## Testing - [x] CI pipeline passes (compile, unit tests, integration tests, static analysis) - [x] Manually tested: built and ran `testing/mss/unit/hal_functionality/test_soc` locally (16 test cases, 44 assertions, all passing) alongside the full existing `ctest` suite (309/309 passing, no regressions); ran a full MISRA C:2025 pass (0 unsuppressed findings, `-DENABLE_SOC_MODULE` added); reformatted and re-verified against the exact clang-format 18.1.3 the CI runner uses; sanity-checked by dropping the `GEMGRSTN` bit from `hal_soc_dss_reset_release()`'s DSSCTL write, confirming the test suite fails (1 assertion), then reverting. - [x] No regressions observed in related areas ## PR Size - [x] XL (> 300 lines) — must split unless exemption declared **Size justification / exemption (if L or XL):** 638 raw lines across 9 files, all hand-reviewed (no mechanically-generated content). Not split further — the driver (`hal_soc.c`/`.h`, 378 lines) and its comprehensive Catch2 spec (`test_soc.c`, 243 lines, covering the bounded-timeout poll paths, secure-vs-general-purpose-part branching, and power-off/power-on sequencing) don't decompose into independently-reviewable sub-PRs, same rationale as prior driver PRs (#78, #80, #82, #84, #86, #88, #90, #92, #94). The remaining files are small CMake/Kconfig/MISRA wiring diffs, also not independently reviewable apart from the driver they enable. ## Checklist - [x] Commit messages follow `type(scope): description` convention with `Relates to #<issue>` footer - [x] PR template filled in completely - [x] No unverified external binaries introduced (see QMS-GITFLOW-001 Binary Security section) - [x] All commits leave the codebase in a compilable, passing-tests state (Commit Integrity Rule) ## Summary - `hal/mss/soc/hal_soc.c`/`.h`: SoC-level bring-up driver (BSS clock init, secure firewall open, DSS reset/halt/unhalt/power-off/power-on) — CP15 MPU configuration out of scope, documented in the header's top-of-file comment - `testing/mss/unit/hal_functionality/test_soc.c` (+ `CMakeLists.txt`): Catch2 functional test suite. No naming collision — no `ti_hal_comparison/test_soc.c` exists (this is SoC-level TOPRCM/DSSREG bring-up logic, not a single register-defined peripheral). - `zephyr/Kconfig` / `zephyr/CMakeLists.txt` / `hal/util/hal_config_mss.h`: `HAL_AWR6843_SOC` Kconfig option and `ENABLE_SOC_MODULE` bridge, same pattern as every other landed driver - `tools/misra/run_misra.sh`: `-DENABLE_SOC_MODULE` added

hoogv added 1 commit

2026-07-23 15:30:43 +00:00

feat(soc): SOC driver implementation and host unit tests

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bceba5b292

Adds hal/mss/soc/hal_soc.c/.h - SoC-level clock/reset bring-up
(TOPRCM/RCM) and DSS power-domain control: BSS clock init with
bounded APLL calibration poll, secure-part-only debug firewall open,
DSS reset release, the common unhalt/halt path, and the full
power-off/power-on protocol with bounded timeouts. CP15 MPU region
configuration is out of scope - see hal_soc.h's top-of-file comment.

Relates to #4, relates to #95

hoogv merged commit bceba5b292 into dev

2026-07-23 15:36:34 +00:00

hoogv added this to the Revision V1.0 Launch milestone

2026-07-23 15:36:38 +00:00

hoogv added this to the Development project

2026-07-23 15:36:40 +00:00

hoogv self-assigned this

2026-07-23 15:36:41 +00:00

hoogv referenced this pull request

2026-07-23 15:41:47 +00:00

feat(mcan): MCAN driver implementation and host unit tests #98

hoogv added the

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