feat: SOC driver implementation and host unit tests #95

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opened 2026-07-23 15:26:24 +00:00 by hoogv · 0 comments

hoogv commented

2026-07-23 15:26:24 +00:00

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Description

Adds hal/mss/soc/hal_soc.c/.h — SoC-level clock/reset bring-up (TOPRCM/RCM) and DSS power-domain control: hal_soc_bss_clock_init() (ungates BSS, polls APLL calibration), hal_soc_secure_firewall_open() (conditionally opens JTAG/logger firewalls on secure parts only), hal_soc_init() (convenience wrapper combining both), hal_soc_dss_reset_release(), hal_soc_dss_unhalt()/hal_soc_dss_halt() (the common bootloader-provided-power-on release/re-halt path), and hal_soc_dss_power_off()/hal_soc_dss_power_on() (the full power-domain-off/on protocol, both correctly bounded-timeout rather than hanging forever on a DSS image that doesn't cooperate).

Deliberately out of scope (documented in hal_soc.h's top-of-file comment): CP15 MPU region configuration — that's ARM-core-coprocessor state, not a TOPRCM/RCM/DSS_REG register, and warrants its own driver.

Use Case / Rationale

As a firmware developer, I need a hal_soc_* API for SoC-level clock bring-up and DSS power-domain sequencing, following the same driver pattern established by GPIO, ESM, UART, I2C, SPI, ADCBUF, CBUFF, HWA, DMM, and EPWM.

As a QMS reviewer, I need a host-native Catch2 test suite (testing/mss/unit/hal_functionality/test_soc.c) covering the bounded-timeout poll paths (both success and timeout), the secure-vs-general-purpose-part branching, and the power-off/power-on sequencing, runnable in CI without target hardware.

Acceptance Criteria

hal/mss/soc/hal_soc.c/.h implemented against this project's current TOPRCM/DSSREG register headers
testing/mss/unit/hal_functionality/test_soc.c passes under ctest
Sanity-checked by deliberately breaking a register field/formula and confirming the test suite catches it, then reverting

Functional Impact

None — self-contained addition alongside the already-landed GPIO/ESM/UART/I2C/SPI/ADCBUF/CBUFF/HWA/DMM/EPWM drivers.

Regulatory Impact

None

QMS Impact

None

Risk Impact

No — existing risk coverage sufficient.

Relates to #4, relates to #75, relates to #77, relates to #79, relates to #81, relates to #83, relates to #85, relates to #87, relates to #89, relates to #91, relates to #93

### Description Adds `hal/mss/soc/hal_soc.c`/`.h` — SoC-level clock/reset bring-up (TOPRCM/RCM) and DSS power-domain control: `hal_soc_bss_clock_init()` (ungates BSS, polls APLL calibration), `hal_soc_secure_firewall_open()` (conditionally opens JTAG/logger firewalls on secure parts only), `hal_soc_init()` (convenience wrapper combining both), `hal_soc_dss_reset_release()`, `hal_soc_dss_unhalt()`/`hal_soc_dss_halt()` (the common bootloader-provided-power-on release/re-halt path), and `hal_soc_dss_power_off()`/`hal_soc_dss_power_on()` (the full power-domain-off/on protocol, both correctly bounded-timeout rather than hanging forever on a DSS image that doesn't cooperate). Deliberately out of scope (documented in `hal_soc.h`'s top-of-file comment): CP15 MPU region configuration — that's ARM-core-coprocessor state, not a TOPRCM/RCM/DSS_REG register, and warrants its own driver. ### Use Case / Rationale As a firmware developer, I need a `hal_soc_*` API for SoC-level clock bring-up and DSS power-domain sequencing, following the same driver pattern established by GPIO, ESM, UART, I2C, SPI, ADCBUF, CBUFF, HWA, DMM, and EPWM. As a QMS reviewer, I need a host-native Catch2 test suite (`testing/mss/unit/hal_functionality/test_soc.c`) covering the bounded-timeout poll paths (both success and timeout), the secure-vs-general-purpose-part branching, and the power-off/power-on sequencing, runnable in CI without target hardware. ### Acceptance Criteria - [ ] `hal/mss/soc/hal_soc.c`/`.h` implemented against this project's current TOPRCM/DSSREG register headers - [ ] `testing/mss/unit/hal_functionality/test_soc.c` passes under `ctest` - [ ] Sanity-checked by deliberately breaking a register field/formula and confirming the test suite catches it, then reverting ### Functional Impact None — self-contained addition alongside the already-landed GPIO/ESM/UART/I2C/SPI/ADCBUF/CBUFF/HWA/DMM/EPWM drivers. ### Regulatory Impact None ### QMS Impact None ### Risk Impact No — existing risk coverage sufficient. ### Related Issues / PRs Relates to #4, relates to #75, relates to #77, relates to #79, relates to #81, relates to #83, relates to #85, relates to #87, relates to #89, relates to #91, relates to #93

hoogv referenced this issue from a commit

2026-07-23 15:30:18 +00:00

feat(soc): SOC driver implementation and host unit tests

hoogv referenced this issue from a pull request that will close it,

2026-07-23 15:30:43 +00:00

feat(soc): SOC driver implementation and host unit tests #96

hoogv closed this issue

2026-07-23 15:36:34 +00:00

hoogv referenced this issue

2026-07-23 15:37:43 +00:00

feat: MCAN driver implementation and host unit tests #97

hoogv self-assigned this