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feat(dss-rti): DSS RTI driver implementation and host unit tests #114

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hoogv merged 1 commit from feat/113-dss-rti-driver into dev

2026-07-23 19:07:03 +00:00

hoogv commented

2026-07-23 19:06:23 +00:00

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Description

Adds hal/dss/rti/hal_dss_rti.c/.h — driver for the two independent DSS-side (C674x) RTI (Real-Time Interrupt) timer instances, DSS_RTIA/DSS_RTIB (TRM Table 4-3's "DSS_RTI (WDT/RTI1)"/"DSS_RTI2", this project's mmwave_sdk-style RTIA/RTIB naming). Neither DSS instance is wired to reset/NMI logic as a watchdog, so this driver — like its scope precedent hal_edma.c — only ever touches counter block 0 / compare channel 0: no watchdog-mode registers, no counter block 1 / compare channels 1-3, no external NTU timebase/capture, no DMA-request wiring.

Provides hal_dss_rti_init(), hal_dss_rti_configure_periodic() (computes RTICPUC0/RTICOMP0/RTIUDCP0 from input_clock_hz/prescale/target_rate_hz), hal_dss_rti_start(), hal_dss_rti_stop(), and hal_dss_rti_clear_interrupt_flag(). The full register bring-up sequence is a 1:1 transcription of example/Barebones_DSS/src/dss_tick_timer.c (sibling AWR6xxx_Toolchain repo), empirically confirmed correct on real AWR6843 silicon — including a documented hardware quirk: RTIUDCP0 must be programmed to the same value as RTICOMP0 (not left at 0), since leaving it at 0 makes the compare-0 interrupt fire exactly once ever instead of periodically.

While implementing, found the driver/test as originally drafted referenced RTISETINTENA/SETINT0 and RTICOMPCTRL.COMPSEL0 — this project's current registers/component/rti.h follows TI's CSL naming instead (RTISETINT/RTICLEARINT, RTICOMPCTRL.COMP0SEL, per that header's own documented cross-check against TI's reg_watchdog.h). Adapted both the driver and its test suite to the current header before landing; caught immediately by a build failure, not silently wrong.

Why

Completes the DSS-side driver batch (Mailbox, EDMA, VIM, DSS ADCBUF, DSS INTC, DSS Cache, DSS HWA already landed) with periodic tick-timer bring-up for the DSS core.

Closes #113

Type of Change

New feature

Impact Assessment

Functional impact: None — self-contained addition alongside the already-landed DSS-side drivers. Completes the DSS-side driver batch.
Regulatory impact: None.
QMS impact: None.
Risk impact: No new risk — the register bring-up sequence is a direct transcription of a hardware-validated reference (not independently derived from the TRM alone), and the documented RTIUDCP0 quirk is carried forward explicitly rather than silently.

Testing

CI pipeline passes (compile, unit tests, integration tests, static analysis)
Manually tested: built and ran testing/dss/rti/test_dss_rti locally (5 test cases, 63 assertions, all passing) alongside the full existing ctest suite (392/392 passing, no regressions); ran a full MISRA C:2025 pass (0 unsuppressed findings, -DENABLE_DSS_RTI_MODULE added); reformatted and re-verified against the exact clang-format 18.1.3 the CI runner uses; sanity-checked by changing hal_dss_rti_configure_periodic()'s RTIUDCP0 write from period back to 0U (undoing the documented hardware-quirk fix), confirming the test suite fails (4 assertions), then reverting.
No regressions observed in related areas

PR Size

XL (> 300 lines) — must split unless exemption declared

Size justification / exemption (if L or XL):

630 raw lines across 6 files, all hand-reviewed (no mechanically-generated content). Not split further — the driver (hal_dss_rti.c/.h, 405 lines, most of it the .h's doc comments explaining the naming cross-reference and the hardware quirk) and its Catch2 spec (test_dss_rti.c, 220 lines) don't decompose into independently-reviewable sub-PRs, same rationale as every prior driver PR in this project. The remaining files are small CMake/MISRA wiring diffs, also not independently reviewable apart from the driver they enable.

Checklist

Commit messages follow type(scope): description convention with Relates to #<issue> footer
PR template filled in completely
No unverified external binaries introduced (see QMS-GITFLOW-001 Binary Security section)
All commits leave the codebase in a compilable, passing-tests state (Commit Integrity Rule)

Summary

hal/dss/rti/hal_dss_rti.c/.h: DSS RTI driver — init/bring-up, periodic-rate configuration, start/stop, interrupt-flag clear, for both DSS_RTIA/DSS_RTIB instances
testing/dss/rti/test_dss_rti.c (+ CMakeLists.txt): Catch2 functional test suite. No naming collision with ti_hal_comparison (that suite's RTI test is test_rti, not test_dss_rti).
testing/CMakeLists.txt: add_subdirectory(dss/rti) and ENABLE_DSS_RTI_MODULE in the shared hw_fakes compile definitions
tools/misra/run_misra.sh: -DENABLE_DSS_RTI_MODULE added

## Description Adds `hal/dss/rti/hal_dss_rti.c`/`.h` — driver for the two independent DSS-side (C674x) RTI (Real-Time Interrupt) timer instances, `DSS_RTIA`/`DSS_RTIB` (TRM Table 4-3's "DSS_RTI (WDT/RTI1)"/"DSS_RTI2", this project's mmwave_sdk-style RTIA/RTIB naming). Neither DSS instance is wired to reset/NMI logic as a watchdog, so this driver — like its scope precedent `hal_edma.c` — only ever touches counter block 0 / compare channel 0: no watchdog-mode registers, no counter block 1 / compare channels 1-3, no external NTU timebase/capture, no DMA-request wiring. Provides `hal_dss_rti_init()`, `hal_dss_rti_configure_periodic()` (computes `RTICPUC0`/`RTICOMP0`/`RTIUDCP0` from `input_clock_hz`/`prescale`/`target_rate_hz`), `hal_dss_rti_start()`, `hal_dss_rti_stop()`, and `hal_dss_rti_clear_interrupt_flag()`. The full register bring-up sequence is a 1:1 transcription of `example/Barebones_DSS/src/dss_tick_timer.c` (sibling `AWR6xxx_Toolchain` repo), empirically confirmed correct on real AWR6843 silicon — including a documented hardware quirk: `RTIUDCP0` must be programmed to the same value as `RTICOMP0` (not left at 0), since leaving it at 0 makes the compare-0 interrupt fire exactly once ever instead of periodically. While implementing, found the driver/test as originally drafted referenced `RTISETINTENA`/`SETINT0` and `RTICOMPCTRL.COMPSEL0` — this project's current `registers/component/rti.h` follows TI's CSL naming instead (`RTISETINT`/`RTICLEARINT`, `RTICOMPCTRL.COMP0SEL`, per that header's own documented cross-check against TI's `reg_watchdog.h`). Adapted both the driver and its test suite to the current header before landing; caught immediately by a build failure, not silently wrong. ## Why Completes the DSS-side driver batch (Mailbox, EDMA, VIM, DSS ADCBUF, DSS INTC, DSS Cache, DSS HWA already landed) with periodic tick-timer bring-up for the DSS core. ## Related Issue Closes #113 ## Type of Change - [x] New feature ## Impact Assessment - **Functional impact:** None — self-contained addition alongside the already-landed DSS-side drivers. Completes the DSS-side driver batch. - **Regulatory impact:** None. - **QMS impact:** None. - **Risk impact:** No new risk — the register bring-up sequence is a direct transcription of a hardware-validated reference (not independently derived from the TRM alone), and the documented RTIUDCP0 quirk is carried forward explicitly rather than silently. ## Testing - [x] CI pipeline passes (compile, unit tests, integration tests, static analysis) - [x] Manually tested: built and ran `testing/dss/rti/test_dss_rti` locally (5 test cases, 63 assertions, all passing) alongside the full existing `ctest` suite (392/392 passing, no regressions); ran a full MISRA C:2025 pass (0 unsuppressed findings, `-DENABLE_DSS_RTI_MODULE` added); reformatted and re-verified against the exact clang-format 18.1.3 the CI runner uses; sanity-checked by changing `hal_dss_rti_configure_periodic()`'s `RTIUDCP0` write from `period` back to `0U` (undoing the documented hardware-quirk fix), confirming the test suite fails (4 assertions), then reverting. - [x] No regressions observed in related areas ## PR Size - [x] XL (> 300 lines) — must split unless exemption declared **Size justification / exemption (if L or XL):** 630 raw lines across 6 files, all hand-reviewed (no mechanically-generated content). Not split further — the driver (`hal_dss_rti.c`/`.h`, 405 lines, most of it the `.h`'s doc comments explaining the naming cross-reference and the hardware quirk) and its Catch2 spec (`test_dss_rti.c`, 220 lines) don't decompose into independently-reviewable sub-PRs, same rationale as every prior driver PR in this project. The remaining files are small CMake/MISRA wiring diffs, also not independently reviewable apart from the driver they enable. ## Checklist - [x] Commit messages follow `type(scope): description` convention with `Relates to #<issue>` footer - [x] PR template filled in completely - [x] No unverified external binaries introduced (see QMS-GITFLOW-001 Binary Security section) - [x] All commits leave the codebase in a compilable, passing-tests state (Commit Integrity Rule) ## Summary - `hal/dss/rti/hal_dss_rti.c`/`.h`: DSS RTI driver — init/bring-up, periodic-rate configuration, start/stop, interrupt-flag clear, for both `DSS_RTIA`/`DSS_RTIB` instances - `testing/dss/rti/test_dss_rti.c` (+ `CMakeLists.txt`): Catch2 functional test suite. No naming collision with `ti_hal_comparison` (that suite's RTI test is `test_rti`, not `test_dss_rti`). - `testing/CMakeLists.txt`: `add_subdirectory(dss/rti)` and `ENABLE_DSS_RTI_MODULE` in the shared `hw_fakes` compile definitions - `tools/misra/run_misra.sh`: `-DENABLE_DSS_RTI_MODULE` added

hoogv added 1 commit

2026-07-23 19:06:23 +00:00

feat(dss-rti): DSS RTI driver implementation and host unit tests

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23b649239c

Adds a driver for the two independent DSS-side (C674x) RTI timer
instances, DSS_RTIA/DSS_RTIB. Neither instance is wired to reset/NMI
logic as a watchdog, so this driver stays scoped to counter block 0
/ compare channel 0 only, matching hal_edma.c's own "explicitly NOT
implemented" precedent. The full bring-up sequence is a 1:1
transcription of a hardware-validated reference
(example/Barebones_DSS/src/dss_tick_timer.c), including a documented
quirk: RTIUDCP0 must equal RTICOMP0, not 0, or the compare-0
interrupt fires exactly once instead of periodically.

Adapted the driver/test against this project's current
registers/component/rti.h, which follows TI's CSL naming
(RTISETINT/RTICLEARINT, RTICOMPCTRL.COMP0SEL) rather than the TRM
prose names the reference implementation used.

Completes the DSS-side driver batch (Mailbox, EDMA, VIM, ADCBUF,
INTC, Cache, HWA, RTI).

Closes #113

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>

hoogv added this to the Revision V1.0 Launch milestone

2026-07-23 19:06:57 +00:00

hoogv added this to the Development project

2026-07-23 19:06:59 +00:00

hoogv self-assigned this

2026-07-23 19:07:00 +00:00

hoogv merged commit 23b649239c into dev

2026-07-23 19:07:03 +00:00

hoogv added the

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