feat: DSS RTI driver implementation and host unit tests #113

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opened 2026-07-23 19:00:48 +00:00 by hoogv · 0 comments

hoogv commented

2026-07-23 19:00:48 +00:00

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Description

Adds hal/dss/rti/hal_dss_rti.c/.h — driver for the two independent DSS-side (C674x) RTI (Real-Time Interrupt) timer instances, DSS_RTIA/DSS_RTIB (TRM Table 4-3's "DSS_RTI (WDT/RTI1)"/"DSS_RTI2", this project's mmwave_sdk-style RTIA/RTIB naming). Same Hercules IP block as the already-landed MSS RTI driver, but neither DSS instance is wired to reset/NMI logic as a watchdog, so this driver — like its scope precedent hal_edma.c — only ever touches counter block 0 / compare channel 0: no watchdog-mode registers, no counter block 1 / compare channels 1-3, no external NTU timebase/capture, no DMA-request wiring.

Provides hal_dss_rti_init(), hal_dss_rti_configure_periodic() (computes RTICPUC0/RTICOMP0/RTIUDCP0 from input_clock_hz/prescale/target_rate_hz), hal_dss_rti_start(), hal_dss_rti_stop(), and hal_dss_rti_clear_interrupt_flag(). The full register bring-up sequence is a 1:1 transcription of example/Barebones_DSS/src/dss_tick_timer.c (sibling AWR6xxx_Toolchain repo), empirically confirmed correct on real AWR6843 silicon — including a documented hardware quirk: RTIUDCP0 must be programmed to the same value as RTICOMP0 (not left at 0), since leaving it at 0 makes the compare-0 interrupt fire exactly once ever instead of periodically, a mistake easy to "simplify away" without having hit this quirk on real hardware.

Use Case / Rationale

As a firmware developer, I need periodic tick-timer bring-up parity on the DSS core with the already-landed MSS RTI driver, generically parameterized rather than hardcoded to the one reference clock/prescale/rate combination dss_tick_timer.c uses.

Acceptance Criteria

hal/dss/rti/hal_dss_rti.c/.h implemented against this project's current hal/registers/component/rti.h/instance/rti.h
testing/dss/rti/test_dss_rti.c passes under ctest
Sanity-checked by deliberately breaking a register field/formula and confirming the test suite catches it, then reverting

Functional Impact

None — self-contained addition alongside the already-landed Mailbox/EDMA/VIM/DSS-ADCBUF/DSS-INTC/DSS-Cache/DSS-HWA drivers. Completes the DSS-side driver batch.

Regulatory Impact

None

QMS Impact

None

Risk Impact

No new risk — the register bring-up sequence is a direct transcription of a hardware-validated reference (not independently derived from the TRM alone), and the documented RTIUDCP0 quirk is carried forward explicitly rather than silently. Existing risk coverage sufficient.

Relates to #4, relates to #99, relates to #101, relates to #103, relates to #105, relates to #107, relates to #109, relates to #111

### Description Adds `hal/dss/rti/hal_dss_rti.c`/`.h` — driver for the two independent DSS-side (C674x) RTI (Real-Time Interrupt) timer instances, `DSS_RTIA`/`DSS_RTIB` (TRM Table 4-3's "DSS_RTI (WDT/RTI1)"/"DSS_RTI2", this project's mmwave_sdk-style RTIA/RTIB naming). Same Hercules IP block as the already-landed MSS RTI driver, but neither DSS instance is wired to reset/NMI logic as a watchdog, so this driver — like its scope precedent `hal_edma.c` — only ever touches counter block 0 / compare channel 0: no watchdog-mode registers, no counter block 1 / compare channels 1-3, no external NTU timebase/capture, no DMA-request wiring. Provides `hal_dss_rti_init()`, `hal_dss_rti_configure_periodic()` (computes `RTICPUC0`/`RTICOMP0`/`RTIUDCP0` from `input_clock_hz`/`prescale`/`target_rate_hz`), `hal_dss_rti_start()`, `hal_dss_rti_stop()`, and `hal_dss_rti_clear_interrupt_flag()`. The full register bring-up sequence is a 1:1 transcription of `example/Barebones_DSS/src/dss_tick_timer.c` (sibling `AWR6xxx_Toolchain` repo), empirically confirmed correct on real AWR6843 silicon — including a documented hardware quirk: `RTIUDCP0` must be programmed to the same value as `RTICOMP0` (not left at 0), since leaving it at 0 makes the compare-0 interrupt fire exactly once ever instead of periodically, a mistake easy to "simplify away" without having hit this quirk on real hardware. ### Use Case / Rationale As a firmware developer, I need periodic tick-timer bring-up parity on the DSS core with the already-landed MSS RTI driver, generically parameterized rather than hardcoded to the one reference clock/prescale/rate combination `dss_tick_timer.c` uses. ### Acceptance Criteria - [ ] `hal/dss/rti/hal_dss_rti.c`/`.h` implemented against this project's current `hal/registers/component/rti.h`/`instance/rti.h` - [ ] `testing/dss/rti/test_dss_rti.c` passes under `ctest` - [ ] Sanity-checked by deliberately breaking a register field/formula and confirming the test suite catches it, then reverting ### Functional Impact None — self-contained addition alongside the already-landed Mailbox/EDMA/VIM/DSS-ADCBUF/DSS-INTC/DSS-Cache/DSS-HWA drivers. Completes the DSS-side driver batch. ### Regulatory Impact None ### QMS Impact None ### Risk Impact No new risk — the register bring-up sequence is a direct transcription of a hardware-validated reference (not independently derived from the TRM alone), and the documented RTIUDCP0 quirk is carried forward explicitly rather than silently. Existing risk coverage sufficient. ### Related Issues / PRs Relates to #4, relates to #99, relates to #101, relates to #103, relates to #105, relates to #107, relates to #109, relates to #111

hoogv referenced this issue from a commit

2026-07-23 19:05:57 +00:00

feat(dss-rti): DSS RTI driver implementation and host unit tests

hoogv referenced this issue from a pull request that will close it,

2026-07-23 19:06:23 +00:00

feat(dss-rti): DSS RTI driver implementation and host unit tests #114

hoogv closed this issue

2026-07-23 19:07:04 +00:00

hoogv added this to the Development project

2026-07-23 19:08:29 +00:00

hoogv added this to the Revision V1.0 Launch milestone

2026-07-23 19:08:31 +00:00