feat(adcbuf): ADCBUF driver implementation and host unit tests

hoogv commented

2026-07-23 13:08:10 +00:00

Owner

Description

Adds hal/mss/adcbuf/hal_adcbuf.c/.h — the ADCBUF driver: channel-enable/real-only/IQ-swap configuration (CFG1), per-channel sample-address configuration (CFG2/CFG3, read-modify-write hazard between paired channels), chirp-count configuration (CFG4), sample-buffer pointer accessor, and ECC enable (polls INITDONE with a bounded timeout) / clear-error for both ping and pong banks. Self-contained — no cross-module dependency.

Why

Continues the driver-implementation phase started by GPIO (#75/#76), ESM (#77/#78), UART (#79/#80), I2C (#81/#82), and SPI (#83/#84).

Closes #85

Type of Change

New feature

Impact Assessment

Functional impact: None — self-contained addition alongside the already-landed GPIO/ESM/UART/I2C/SPI drivers.
Regulatory impact: None.
QMS impact: None.
Risk impact: No — existing risk coverage sufficient.

Testing

CI pipeline passes (compile, unit tests, integration tests, static analysis)
Manually tested: built and ran testing/mss/unit/hal_functionality/test_adcbuf_functional locally (13 test cases, 59 assertions, all passing, plus 10 repeated back-to-back runs to confirm the threaded ECC-init-done simulation isn't flaky) alongside the full existing ctest suite (235/235 passing, no regressions); ran a full MISRA C:2025 pass (0 unsuppressed findings, -DENABLE_ADCBUF_MODULE added); reformatted and re-verified against the exact clang-format 18.1.3 the CI runner uses; sanity-checked by swapping the RX0 branch to set RX1EN instead of RX0EN, confirming the test suite fails (4 assertions), then reverting.
No regressions observed in related areas

PR Size

XL (> 300 lines) — justification required below

Size justification / exemption (if L or XL):

636 raw lines across 6 files, all hand-reviewed (no mechanically-generated content). Not split further — the driver (hal_adcbuf.c/.h, 324 lines) and its comprehensive Catch2 spec (test_adcbuf.c, 305 lines, covering channel config, address RMW isolation, and the threaded ECC init/enable sequence) don't decompose into independently-reviewable sub-PRs, same rationale as prior driver PRs (#78, #80, #82, #84).

Checklist

Commit messages follow type(scope): description convention with Relates to #<issue> footer
PR template filled in completely
No unverified external binaries introduced (see QMS-GITFLOW-001 Binary Security section)
All commits leave the codebase in a compilable, passing-tests state (Commit Integrity Rule)

Summary

hal/mss/adcbuf/hal_adcbuf.c/.h: ADCBUF driver (channel/address/chirp-count config, sample-buffer accessor, ECC enable/clear-error)
testing/mss/unit/hal_functionality/test_adcbuf.c (+ CMakeLists.txt): Catch2 functional test suite, using a background std::thread to simulate the ECC-init-done hardware state machine (verified stable across 10 repeated runs, not flaky)
tools/misra/run_misra.sh: -DENABLE_ADCBUF_MODULE added

## Description Adds `hal/mss/adcbuf/hal_adcbuf.c`/`.h` — the ADCBUF driver: channel-enable/real-only/IQ-swap configuration (`CFG1`), per-channel sample-address configuration (`CFG2`/`CFG3`, read-modify-write hazard between paired channels), chirp-count configuration (`CFG4`), sample-buffer pointer accessor, and ECC enable (polls `INITDONE` with a bounded timeout) / clear-error for both ping and pong banks. Self-contained — no cross-module dependency. ## Why Continues the driver-implementation phase started by GPIO (#75/#76), ESM (#77/#78), UART (#79/#80), I2C (#81/#82), and SPI (#83/#84). ## Related Issue Closes #85 ## Type of Change - [x] New feature ## Impact Assessment - **Functional impact:** None — self-contained addition alongside the already-landed GPIO/ESM/UART/I2C/SPI drivers. - **Regulatory impact:** None. - **QMS impact:** None. - **Risk impact:** No — existing risk coverage sufficient. ## Testing - [x] CI pipeline passes (compile, unit tests, integration tests, static analysis) - [x] Manually tested: built and ran `testing/mss/unit/hal_functionality/test_adcbuf_functional` locally (13 test cases, 59 assertions, all passing, plus 10 repeated back-to-back runs to confirm the threaded ECC-init-done simulation isn't flaky) alongside the full existing `ctest` suite (235/235 passing, no regressions); ran a full MISRA C:2025 pass (0 unsuppressed findings, `-DENABLE_ADCBUF_MODULE` added); reformatted and re-verified against the exact clang-format 18.1.3 the CI runner uses; sanity-checked by swapping the RX0 branch to set `RX1EN` instead of `RX0EN`, confirming the test suite fails (4 assertions), then reverting. - [x] No regressions observed in related areas ## PR Size - [x] XL (> 300 lines) — justification required below **Size justification / exemption (if L or XL):** 636 raw lines across 6 files, all hand-reviewed (no mechanically-generated content). Not split further — the driver (`hal_adcbuf.c`/`.h`, 324 lines) and its comprehensive Catch2 spec (`test_adcbuf.c`, 305 lines, covering channel config, address RMW isolation, and the threaded ECC init/enable sequence) don't decompose into independently-reviewable sub-PRs, same rationale as prior driver PRs (#78, #80, #82, #84). ## Checklist - [x] Commit messages follow `type(scope): description` convention with `Relates to #<issue>` footer - [x] PR template filled in completely - [x] No unverified external binaries introduced (see QMS-GITFLOW-001 Binary Security section) - [x] All commits leave the codebase in a compilable, passing-tests state (Commit Integrity Rule) ## Summary - `hal/mss/adcbuf/hal_adcbuf.c`/`.h`: ADCBUF driver (channel/address/chirp-count config, sample-buffer accessor, ECC enable/clear-error) - `testing/mss/unit/hal_functionality/test_adcbuf.c` (+ `CMakeLists.txt`): Catch2 functional test suite, using a background `std::thread` to simulate the ECC-init-done hardware state machine (verified stable across 10 repeated runs, not flaky) - `tools/misra/run_misra.sh`: `-DENABLE_ADCBUF_MODULE` added

hoogv added 1 commit

2026-07-23 13:08:10 +00:00

feat(adcbuf): ADCBUF driver implementation and host unit tests

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8e88f6c3a1

Adds hal/mss/adcbuf/hal_adcbuf.c/.h -- channel-enable/real-only/IQ-swap
configuration via a plain CFG1 write (WRITEMODE/CONTMODEEN/CONTSTRTPL/
CONTSTOPPL deliberately left unexposed, at their reset value),
per-channel sample-address configuration via CFG2/CFG3 (a genuine
read-modify-write hazard since RX0/RX1 share CFG2 and RX2/RX3 share
CFG3), chirp-count configuration via a plain CFG4 write, a sample-
buffer pointer accessor, and ECC enable (polls INITDONE with a bounded
timeout, same reasoning as hal_soc.c's APLL_CAL_TIMEOUT_ITERATIONS) /
clear-error for both ping and pong banks. Self-contained, no
cross-module dependency.

Reformatted and verified against the exact clang-format 18.1.3 the CI
runner uses.

testing/mss/unit/hal_functionality/test_adcbuf.c uses a background
std::thread to simulate the ECC-init-done hardware state machine
(std::thread + atomic fetch-or, since a plain-write fake can't model a
trigger bit that clears itself asynchronously) -- ran it 10 times back
to back locally to confirm the timing is stable, not flaky, before
trusting it in CI.

Verified clean under that suite (13 test cases, 59 assertions) plus
the full existing suite (235/235), and a MISRA C:2025 pass (0
findings, -DENABLE_ADCBUF_MODULE added).

Sanity-checked by swapping hal_adcbuf_configure()'s RX0 branch to set
RX1EN instead of RX0EN, confirming test_adcbuf_functional fails (4
assertions), then reverting.

Closes #85

Signed-off-by: Victor Hogeweij <hogeweyv@gmail.com>

hoogv added the

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feat(adcbuf): ADCBUF driver implementation and host unit tests #86

Description

Why

Related Issue

Type of Change

Impact Assessment

Testing

PR Size

Checklist

Summary