feat: Mailbox driver implementation and host unit tests #99

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opened 2026-07-23 16:08:30 +00:00 by hoogv · 0 comments

hoogv commented

2026-07-23 16:08:30 +00:00

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Description

Adds hal/dss/hal_mailbox/hal_mailbox.c/.h — the inter-processor Mailbox driver (MSS's point of view, covering both the MSS<->BSS and MSS<->DSS links): hal_mailbox_send() (copies a message into the outgoing direction's shared memory, raises the "new message" doorbell), hal_mailbox_message_pending(), hal_mailbox_receive() (copies out of the incoming direction's shared memory, acknowledges via INT_ACK, then raises the "message consumed" doorbell on the same incoming block), and the four raw device handlers (MBOX_MSS_DSS_BOX_FULL_IRQHandler/MBOX_MSS_DSS_BOX_EMPTY_IRQHandler/MBOX_MSS_BSS_BOX_FULL_IRQHandler/MBOX_MSS_BSS_BOX_EMPTY_IRQHandler) decoding/clearing the CPU interrupt condition to a weak, application-overridable hal_mailbox_irq_handler() hook.

This is the first driver of a second, DSS-side driver batch — landing Mailbox first since hal_vim.c's dispatch table (already merged, header-only pending this) references its four MBOX_* handler symbols directly.

Use Case / Rationale

As a firmware developer, I need a hal_mailbox_* API for inter-processor message passing between MSS and DSS/BSS, following the same driver pattern established by the MSS-side driver batch (GPIO through MCAN).

As a QMS reviewer, I need a host-native Catch2 test suite (testing/dss/hal_mailbox/test_mailbox.c) covering both links' send/receive/pending paths and all four IRQ handlers' correct register-block resolution, runnable in CI without target hardware.

Acceptance Criteria

hal/dss/hal_mailbox/hal_mailbox.c/.h implemented against this project's current hal/registers/component/mailbox.h/instance/mailbox.h
testing/dss/hal_mailbox/test_mailbox.c passes under ctest
Sanity-checked by deliberately breaking a register field/formula and confirming the test suite catches it, then reverting

Functional Impact

None — self-contained addition; first DSS-side driver, no interaction with already-landed MSS drivers beyond shared test infrastructure.

Regulatory Impact

None

QMS Impact

None

Risk Impact

No — existing risk coverage sufficient.

Relates to #4

### Description Adds `hal/dss/hal_mailbox/hal_mailbox.c`/`.h` — the inter-processor Mailbox driver (MSS's point of view, covering both the MSS<->BSS and MSS<->DSS links): `hal_mailbox_send()` (copies a message into the outgoing direction's shared memory, raises the "new message" doorbell), `hal_mailbox_message_pending()`, `hal_mailbox_receive()` (copies out of the incoming direction's shared memory, acknowledges via INT_ACK, then raises the "message consumed" doorbell on the same incoming block), and the four raw device handlers (`MBOX_MSS_DSS_BOX_FULL_IRQHandler`/`MBOX_MSS_DSS_BOX_EMPTY_IRQHandler`/`MBOX_MSS_BSS_BOX_FULL_IRQHandler`/`MBOX_MSS_BSS_BOX_EMPTY_IRQHandler`) decoding/clearing the CPU interrupt condition to a weak, application-overridable `hal_mailbox_irq_handler()` hook. This is the first driver of a second, DSS-side driver batch — landing Mailbox first since `hal_vim.c`'s dispatch table (already merged, header-only pending this) references its four `MBOX_*` handler symbols directly. ### Use Case / Rationale As a firmware developer, I need a `hal_mailbox_*` API for inter-processor message passing between MSS and DSS/BSS, following the same driver pattern established by the MSS-side driver batch (GPIO through MCAN). As a QMS reviewer, I need a host-native Catch2 test suite (`testing/dss/hal_mailbox/test_mailbox.c`) covering both links' send/receive/pending paths and all four IRQ handlers' correct register-block resolution, runnable in CI without target hardware. ### Acceptance Criteria - [ ] `hal/dss/hal_mailbox/hal_mailbox.c`/`.h` implemented against this project's current `hal/registers/component/mailbox.h`/`instance/mailbox.h` - [ ] `testing/dss/hal_mailbox/test_mailbox.c` passes under `ctest` - [ ] Sanity-checked by deliberately breaking a register field/formula and confirming the test suite catches it, then reverting ### Functional Impact None — self-contained addition; first DSS-side driver, no interaction with already-landed MSS drivers beyond shared test infrastructure. ### Regulatory Impact None ### QMS Impact None ### Risk Impact No — existing risk coverage sufficient. ### Related Issues / PRs Relates to #4

hoogv referenced this issue from a commit

2026-07-23 18:08:42 +00:00

feat(mailbox): Mailbox driver implementation and host unit tests

hoogv referenced this issue from a pull request that will close it,

2026-07-23 18:09:13 +00:00

feat(mailbox): Mailbox driver implementation and host unit tests #100

hoogv closed this issue

2026-07-23 18:10:09 +00:00

hoogv referenced this issue

2026-07-23 18:11:00 +00:00

feat: EDMA driver implementation and host unit tests #101

hoogv referenced this issue from a commit