feat: DSS ADCBUF driver implementation and host unit tests #105

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opened 2026-07-23 18:28:40 +00:00 by hoogv · 0 comments

hoogv commented

2026-07-23 18:28:40 +00:00

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Description

Adds hal/dss/adcbuf/hal_dss_adcbuf.c/.h — the DSS-side counterpart of the already-landed MSS ADCBUF driver (#85/#86). ADCBUF is physically dual-mapped (same register block and sample-data memory window visible at different base addresses depending on which core accesses them), so this driver targets the DSS-visible DSS_ADCBUF_CFG/DSS_ADCBUF_ECC/DSS_ADCBUF_MEM addresses with the identical register semantics and functional scope as the MSS driver: channel-enable/real-only/IQ-swap configuration, per-channel sample-address configuration (read-modify-write-guarded), chirp-count configuration, sample-buffer pointer accessor, and ECC enable (bounded INITDONE poll)/clear-error for both ping and pong banks.

Does not configure the radar front end (BSS) that performs the actual analog-to-digital conversion — that's a separate subsystem reached over mailbox/mmWaveLink-style messaging, out of scope for this HAL.

Use Case / Rationale

As a firmware developer, I need a DSS-side hal_dss_adcbuf_* API mirroring the MSS one, continuing the DSS-side driver batch (Mailbox, EDMA, VIM already landed).

As a QMS reviewer, I need a host-native Catch2 test suite (testing/dss/adcbuf/test_dss_adcbuf.c) covering channel configuration, address read-modify-write isolation, and the ECC init/enable sequence, runnable in CI without target hardware — same coverage shape as the MSS driver's own test suite.

Acceptance Criteria

hal/dss/adcbuf/hal_dss_adcbuf.c/.h implemented against this project's current hal/registers/component/adcbuf.h/instance/adcbuf.h
testing/dss/adcbuf/test_dss_adcbuf.c passes under ctest
Sanity-checked by deliberately breaking a register field/formula and confirming the test suite catches it, then reverting

Functional Impact

None — self-contained addition alongside the already-landed Mailbox/EDMA/VIM drivers.

Regulatory Impact

None

QMS Impact

None

Risk Impact

No — existing risk coverage sufficient.

Relates to #4, relates to #85, relates to #99, relates to #101, relates to #103

### Description Adds `hal/dss/adcbuf/hal_dss_adcbuf.c`/`.h` — the DSS-side counterpart of the already-landed MSS ADCBUF driver (#85/#86). ADCBUF is physically dual-mapped (same register block and sample-data memory window visible at different base addresses depending on which core accesses them), so this driver targets the DSS-visible `DSS_ADCBUF_CFG`/`DSS_ADCBUF_ECC`/`DSS_ADCBUF_MEM` addresses with the identical register semantics and functional scope as the MSS driver: channel-enable/real-only/IQ-swap configuration, per-channel sample-address configuration (read-modify-write-guarded), chirp-count configuration, sample-buffer pointer accessor, and ECC enable (bounded `INITDONE` poll)/clear-error for both ping and pong banks. Does not configure the radar front end (BSS) that performs the actual analog-to-digital conversion — that's a separate subsystem reached over mailbox/mmWaveLink-style messaging, out of scope for this HAL. ### Use Case / Rationale As a firmware developer, I need a DSS-side `hal_dss_adcbuf_*` API mirroring the MSS one, continuing the DSS-side driver batch (Mailbox, EDMA, VIM already landed). As a QMS reviewer, I need a host-native Catch2 test suite (`testing/dss/adcbuf/test_dss_adcbuf.c`) covering channel configuration, address read-modify-write isolation, and the ECC init/enable sequence, runnable in CI without target hardware — same coverage shape as the MSS driver's own test suite. ### Acceptance Criteria - [ ] `hal/dss/adcbuf/hal_dss_adcbuf.c`/`.h` implemented against this project's current `hal/registers/component/adcbuf.h`/`instance/adcbuf.h` - [ ] `testing/dss/adcbuf/test_dss_adcbuf.c` passes under `ctest` - [ ] Sanity-checked by deliberately breaking a register field/formula and confirming the test suite catches it, then reverting ### Functional Impact None — self-contained addition alongside the already-landed Mailbox/EDMA/VIM drivers. ### Regulatory Impact None ### QMS Impact None ### Risk Impact No — existing risk coverage sufficient. ### Related Issues / PRs Relates to #4, relates to #85, relates to #99, relates to #101, relates to #103

hoogv referenced this issue from a commit

2026-07-23 18:32:57 +00:00

feat(dss-adcbuf): DSS ADCBUF driver implementation and host unit tests

hoogv referenced this issue from a pull request that will close it,

2026-07-23 18:33:25 +00:00

feat(dss-adcbuf): DSS ADCBUF driver implementation and host unit tests #106

hoogv closed this issue

2026-07-23 18:35:02 +00:00

hoogv referenced this issue

2026-07-23 18:37:18 +00:00

feat: DSS INTC driver implementation and host unit tests #107

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