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feat(dss-adcbuf): DSS ADCBUF driver implementation and host unit tests #106

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hoogv merged 1 commit from feat/105-dss-adcbuf-driver into dev

2026-07-23 18:35:01 +00:00

hoogv commented

2026-07-23 18:33:25 +00:00

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Description

Adds hal/dss/adcbuf/hal_dss_adcbuf.c/.h — the DSS-side counterpart of the already-landed MSS ADCBUF driver (#85/#86). ADCBUF is physically dual-mapped (same register block and sample-data memory window visible at different base addresses depending on which core accesses them), so this driver targets the DSS-visible DSS_ADCBUF_CFG/DSS_ADCBUF_ECC/DSS_ADCBUF_MEM addresses with the identical register semantics and functional scope as the MSS driver: channel-enable/real-only/IQ-swap configuration, per-channel sample-address configuration (read-modify-write-guarded), chirp-count configuration, sample-buffer pointer accessor, and ECC enable (bounded INITDONE poll)/clear-error for both ping and pong banks. Self-contained — no cross-module dependency.

Why

Continues the DSS-side driver batch (Mailbox, EDMA, VIM already landed).

Closes #105

Type of Change

New feature

Impact Assessment

Functional impact: None — self-contained addition alongside the already-landed Mailbox/EDMA/VIM drivers.
Regulatory impact: None.
QMS impact: None.
Risk impact: No — existing risk coverage sufficient.

Testing

CI pipeline passes (compile, unit tests, integration tests, static analysis)
Manually tested: built and ran testing/dss/adcbuf/test_dss_adcbuf locally (13 test cases, 59 assertions, all passing) alongside the full existing ctest suite (366/366 passing, no regressions); ran a full MISRA C:2025 pass (0 unsuppressed findings, -DENABLE_DSS_ADCBUF_MODULE added); reformatted and re-verified against the exact clang-format 18.1.3 the CI runner uses; sanity-checked by swapping RX0's CFG2 mask from ADCBUFADDRX0_Msk to ADCBUFADDRX1_Msk in hal_dss_adcbuf_set_channel_address(), confirming the test suite fails (1 assertion), then reverting.
No regressions observed in related areas

PR Size

XL (> 300 lines) — must split unless exemption declared

Size justification / exemption (if L or XL):

618 raw lines across 6 files, all hand-reviewed (no mechanically-generated content). Not split further — the driver (hal_dss_adcbuf.c/.h, 337 lines) and its comprehensive Catch2 spec (test_dss_adcbuf.c, 276 lines, covering channel configuration, address read-modify-write isolation, and the ECC init/enable sequence) don't decompose into independently-reviewable sub-PRs, same rationale as every prior driver PR in this project. The remaining files are small CMake/MISRA wiring diffs, also not independently reviewable apart from the driver they enable.

Checklist

Commit messages follow type(scope): description convention with Relates to #<issue> footer
PR template filled in completely
No unverified external binaries introduced (see QMS-GITFLOW-001 Binary Security section)
All commits leave the codebase in a compilable, passing-tests state (Commit Integrity Rule)

Summary

hal/dss/adcbuf/hal_dss_adcbuf.c/.h: DSS ADCBUF driver — DSS-side counterpart of hal_adcbuf.c, same register semantics/functional scope, targeting DSS_ADCBUF_CFG/DSS_ADCBUF_ECC/DSS_ADCBUF_MEM
testing/dss/adcbuf/test_dss_adcbuf.c (+ CMakeLists.txt): Catch2 functional test suite. No naming collision with ti_hal_comparison (that suite's ADCBUF test is test_adcbuf, not test_dss_adcbuf).
testing/CMakeLists.txt: add_subdirectory(dss/adcbuf) and ENABLE_DSS_ADCBUF_MODULE in the shared hw_fakes compile definitions
tools/misra/run_misra.sh: -DENABLE_DSS_ADCBUF_MODULE added

## Description Adds `hal/dss/adcbuf/hal_dss_adcbuf.c`/`.h` — the DSS-side counterpart of the already-landed MSS ADCBUF driver (#85/#86). ADCBUF is physically dual-mapped (same register block and sample-data memory window visible at different base addresses depending on which core accesses them), so this driver targets the DSS-visible `DSS_ADCBUF_CFG`/`DSS_ADCBUF_ECC`/`DSS_ADCBUF_MEM` addresses with the identical register semantics and functional scope as the MSS driver: channel-enable/real-only/IQ-swap configuration, per-channel sample-address configuration (read-modify-write-guarded), chirp-count configuration, sample-buffer pointer accessor, and ECC enable (bounded `INITDONE` poll)/clear-error for both ping and pong banks. Self-contained — no cross-module dependency. ## Why Continues the DSS-side driver batch (Mailbox, EDMA, VIM already landed). ## Related Issue Closes #105 ## Type of Change - [x] New feature ## Impact Assessment - **Functional impact:** None — self-contained addition alongside the already-landed Mailbox/EDMA/VIM drivers. - **Regulatory impact:** None. - **QMS impact:** None. - **Risk impact:** No — existing risk coverage sufficient. ## Testing - [x] CI pipeline passes (compile, unit tests, integration tests, static analysis) - [x] Manually tested: built and ran `testing/dss/adcbuf/test_dss_adcbuf` locally (13 test cases, 59 assertions, all passing) alongside the full existing `ctest` suite (366/366 passing, no regressions); ran a full MISRA C:2025 pass (0 unsuppressed findings, `-DENABLE_DSS_ADCBUF_MODULE` added); reformatted and re-verified against the exact clang-format 18.1.3 the CI runner uses; sanity-checked by swapping RX0's CFG2 mask from `ADCBUFADDRX0_Msk` to `ADCBUFADDRX1_Msk` in `hal_dss_adcbuf_set_channel_address()`, confirming the test suite fails (1 assertion), then reverting. - [x] No regressions observed in related areas ## PR Size - [x] XL (> 300 lines) — must split unless exemption declared **Size justification / exemption (if L or XL):** 618 raw lines across 6 files, all hand-reviewed (no mechanically-generated content). Not split further — the driver (`hal_dss_adcbuf.c`/`.h`, 337 lines) and its comprehensive Catch2 spec (`test_dss_adcbuf.c`, 276 lines, covering channel configuration, address read-modify-write isolation, and the ECC init/enable sequence) don't decompose into independently-reviewable sub-PRs, same rationale as every prior driver PR in this project. The remaining files are small CMake/MISRA wiring diffs, also not independently reviewable apart from the driver they enable. ## Checklist - [x] Commit messages follow `type(scope): description` convention with `Relates to #<issue>` footer - [x] PR template filled in completely - [x] No unverified external binaries introduced (see QMS-GITFLOW-001 Binary Security section) - [x] All commits leave the codebase in a compilable, passing-tests state (Commit Integrity Rule) ## Summary - `hal/dss/adcbuf/hal_dss_adcbuf.c`/`.h`: DSS ADCBUF driver — DSS-side counterpart of `hal_adcbuf.c`, same register semantics/functional scope, targeting `DSS_ADCBUF_CFG`/`DSS_ADCBUF_ECC`/`DSS_ADCBUF_MEM` - `testing/dss/adcbuf/test_dss_adcbuf.c` (+ `CMakeLists.txt`): Catch2 functional test suite. No naming collision with `ti_hal_comparison` (that suite's ADCBUF test is `test_adcbuf`, not `test_dss_adcbuf`). - `testing/CMakeLists.txt`: `add_subdirectory(dss/adcbuf)` and `ENABLE_DSS_ADCBUF_MODULE` in the shared `hw_fakes` compile definitions - `tools/misra/run_misra.sh`: `-DENABLE_DSS_ADCBUF_MODULE` added

hoogv added 1 commit

2026-07-23 18:33:25 +00:00

feat(dss-adcbuf): DSS ADCBUF driver implementation and host unit tests

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72852b8ec1

Adds hal/dss/adcbuf/hal_dss_adcbuf.c/.h - the DSS-side counterpart of
the already-landed MSS ADCBUF driver. ADCBUF is physically dual-mapped
(same register block and sample-data memory visible at different base
addresses per core), so this targets DSS_ADCBUF_CFG/ECC/MEM with
identical register semantics and functional scope to the MSS driver.

Relates to #4, relates to #85, relates to #99, relates to #101, relates to #103, relates to #105

hoogv added this to the Revision V1.0 Launch milestone

2026-07-23 18:34:56 +00:00

hoogv added this to the Development project

2026-07-23 18:34:57 +00:00

hoogv self-assigned this

2026-07-23 18:34:59 +00:00

hoogv merged commit 72852b8ec1 into dev

2026-07-23 18:35:01 +00:00

hoogv added the

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