feat(i2c): I2C host-mode driver implementation and host unit tests #82

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hoogv merged 1 commit from feat/81-i2c-driver into dev 2026-07-23 12:41:39 +00:00
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Description

Adds hal/mss/i2c_host/hal_i2c_host.c/.h — the I2C driver: prescaler/clock derivation (TRM-derived module-clock search + ICCL/ICCH split), blocking write/read with per-byte and transfer-complete poll loops, NACK/arbitration-lost error reporting, and the IRQ handler decoding ICSTR to a weak, application-overridable hal_i2c_host_irq_handler() hook. Self-contained — no cross-module dependency.

Why

Continues the driver-implementation phase started by GPIO (#75/#76), ESM (#77/#78), and UART (#79/#80).

Closes #81

Type of Change

  • New feature

Impact Assessment

  • Functional impact: None — self-contained addition alongside the already-landed GPIO/ESM/UART drivers.
  • Regulatory impact: None.
  • QMS impact: None.
  • Risk impact: No — existing risk coverage sufficient.

Testing

  • CI pipeline passes (compile, unit tests, integration tests, static analysis)
  • Manually tested: built and ran testing/mss/unit/hal_functionality/test_i2c_host locally (16 test cases, 67 assertions, all passing) alongside the full existing ctest suite (205/205 passing, no regressions); ran a full MISRA C:2025 pass (0 unsuppressed findings, -DENABLE_I2C_HOST_MODULE added); reformatted and re-verified against the exact clang-format 18.1.3 the CI runner uses; sanity-checked by off-by-one-ing the ICCL/ICCH divisor computation, confirming the test suite fails (6 assertions), then reverting.
  • No regressions observed in related areas

PR Size

  • XL (> 300 lines) — justification required below

Size justification / exemption (if L or XL):

959 raw lines across 6 files, all hand-reviewed (no mechanically-generated content). Not split further — the driver (hal_i2c_host.c/.h, 581 lines) and its comprehensive Catch2 spec (test_i2c_host.c, 371 lines, covering clock derivation, both transfer directions, and error paths) don't decompose into independently-reviewable sub-PRs, same rationale as ESM's (#78) and UART's (#80) PRs.

Checklist

  • Commit messages follow type(scope): description convention with Relates to #<issue> footer
  • PR template filled in completely
  • No unverified external binaries introduced (see QMS-GITFLOW-001 Binary Security section)
  • All commits leave the codebase in a compilable, passing-tests state (Commit Integrity Rule)

Summary

  • hal/mss/i2c_host/hal_i2c_host.c/.h: I2C driver (clock derivation, blocking write/read, error reporting, IRQ handler)
  • Cross-checked the clock-prescaler/divisor formula against TI's own ti/drivers/i2c/src/i2c_reg.c (I2CMasterInitClk) — TI hardcodes an 8MHz internal-clock target and fixed d=5, this driver derives both per the TRM's full generality; both agree structurally for this SoC's actual 200MHz VCLK, no correction needed
  • testing/mss/unit/hal_functionality/test_i2c_host.c (+ CMakeLists.txt): Catch2 functional test suite
  • tools/misra/run_misra.sh: -DENABLE_I2C_HOST_MODULE added
## Description Adds `hal/mss/i2c_host/hal_i2c_host.c`/`.h` — the I2C driver: prescaler/clock derivation (TRM-derived module-clock search + `ICCL`/`ICCH` split), blocking write/read with per-byte and transfer-complete poll loops, NACK/arbitration-lost error reporting, and the IRQ handler decoding `ICSTR` to a weak, application-overridable `hal_i2c_host_irq_handler()` hook. Self-contained — no cross-module dependency. ## Why Continues the driver-implementation phase started by GPIO (#75/#76), ESM (#77/#78), and UART (#79/#80). ## Related Issue Closes #81 ## Type of Change - [x] New feature ## Impact Assessment - **Functional impact:** None — self-contained addition alongside the already-landed GPIO/ESM/UART drivers. - **Regulatory impact:** None. - **QMS impact:** None. - **Risk impact:** No — existing risk coverage sufficient. ## Testing - [x] CI pipeline passes (compile, unit tests, integration tests, static analysis) - [x] Manually tested: built and ran `testing/mss/unit/hal_functionality/test_i2c_host` locally (16 test cases, 67 assertions, all passing) alongside the full existing `ctest` suite (205/205 passing, no regressions); ran a full MISRA C:2025 pass (0 unsuppressed findings, `-DENABLE_I2C_HOST_MODULE` added); reformatted and re-verified against the exact clang-format 18.1.3 the CI runner uses; sanity-checked by off-by-one-ing the `ICCL`/`ICCH` divisor computation, confirming the test suite fails (6 assertions), then reverting. - [x] No regressions observed in related areas ## PR Size - [x] XL (> 300 lines) — justification required below **Size justification / exemption (if L or XL):** 959 raw lines across 6 files, all hand-reviewed (no mechanically-generated content). Not split further — the driver (`hal_i2c_host.c`/`.h`, 581 lines) and its comprehensive Catch2 spec (`test_i2c_host.c`, 371 lines, covering clock derivation, both transfer directions, and error paths) don't decompose into independently-reviewable sub-PRs, same rationale as ESM's (#78) and UART's (#80) PRs. ## Checklist - [x] Commit messages follow `type(scope): description` convention with `Relates to #<issue>` footer - [x] PR template filled in completely - [x] No unverified external binaries introduced (see QMS-GITFLOW-001 Binary Security section) - [x] All commits leave the codebase in a compilable, passing-tests state (Commit Integrity Rule) ## Summary - `hal/mss/i2c_host/hal_i2c_host.c`/`.h`: I2C driver (clock derivation, blocking write/read, error reporting, IRQ handler) - Cross-checked the clock-prescaler/divisor formula against TI's own `ti/drivers/i2c/src/i2c_reg.c` (`I2CMasterInitClk`) — TI hardcodes an 8MHz internal-clock target and fixed `d=5`, this driver derives both per the TRM's full generality; both agree structurally for this SoC's actual 200MHz VCLK, no correction needed - `testing/mss/unit/hal_functionality/test_i2c_host.c` (+ `CMakeLists.txt`): Catch2 functional test suite - `tools/misra/run_misra.sh`: `-DENABLE_I2C_HOST_MODULE` added
feat(i2c): I2C host-mode driver implementation and host unit tests
All checks were successful
tests / host-tests (pull_request) Successful in 57s
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tests / host-tests (push) Successful in 56s
2e57961b54
Adds hal/mss/i2c_host/hal_i2c_host.c/.h -- prescaler/clock derivation
(searches upward for the smallest ICPSC bringing the module clock at
or below the TRM's 13.3MHz ceiling, then splits the ICCL/ICCH divisor
evenly using the TRM's variable per-ICPSC offset d), blocking write/
read with per-byte (ICXRDY/ICRRDY) and transfer-complete (BB) poll
loops, NACK/arbitration-lost error reporting, and the IRQ handler
decoding ICSTR to a weak, application-overridable
hal_i2c_host_irq_handler() hook. Self-contained, no cross-module
dependency. This is a from-scratch Hercules-family I2C module, not
ported from an existing Universal_hal driver (unlike SPI, per the
driver's own top-of-file comment).

Ported from a prior local draft, reformatted and verified against the
exact clang-format 18.1.3 the CI runner uses (pulled from the
ccstudio image directly). Cross-checked the clock-prescaler/divisor
formula against TI's own ti/drivers/i2c/src/i2c_reg.c
(I2CMasterInitClk) -- TI hardcodes an 8MHz internal-clock target and a
fixed d=5 offset, whereas this driver derives both per the TRM's full
generality (variable ICPSC search, variable d for ICPSC 0/1/>1); for
this SoC's actual 200MHz VCLK both land in the same d=5 regime and
agree structurally, so no correction needed.

Verified clean under testing/mss/unit/hal_functionality/test_i2c_host.c
(16 test cases, 67 assertions) plus the full existing suite (205/205),
and a MISRA C:2025 pass (0 findings, -DENABLE_I2C_HOST_MODULE added).

Sanity-checked by off-by-one-ing hal_i2c_host_init()'s ICCL/ICCH
divisor computation, confirming test_i2c_host fails (6 assertions),
then reverting.

Closes #81

Signed-off-by: Victor Hogeweij <hogeweyv@gmail.com>
hoogv added this to the Development project 2026-07-23 12:42:15 +00:00
hoogv self-assigned this 2026-07-23 13:36:13 +00:00
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