feat: UART (SCI) driver implementation and host unit tests #79

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opened 2026-07-23 11:29:57 +00:00 by hoogv · 0 comments

hoogv commented

2026-07-23 11:29:57 +00:00

(Migrated from codeberg.org)

Description

Adds hal/mss/uart/hal_uart.c/.h — the UART (SCI) driver: baud/parity/stop-bit init (TRM-derived divisor formula against the 200MHz VCLK), blocking transmit/receive with bounded ready-poll timeouts, IRQ source enable/disable/priority, and the four instance/priority-line raw handlers decoding SCIFLR to a weak, application-overridable hal_uart_irq_handler() hook.

Use Case / Rationale

As a firmware developer, I need a hal_uart_* API for blocking UART I/O and IRQ configuration, following the same driver pattern established by GPIO (#75) and ESM (#77).

As a QMS reviewer, I need the baud-divisor formula's correctness (and its two representative divisor values) covered by an automated test, the same rigor already applied to GPIO/ESM.

User Stories

As a developer, I want hal_uart_init() to compute SCIBAUD from a requested bit rate instead of hand-computing the TRM formula myself.
As a developer, I want hal_uart_transmit()/hal_uart_receive() to block with a bounded timeout rather than spin forever on a stuck/absent SCI.
As a QMS reviewer, I want a host-native Catch2 test suite (testing/mss/unit/hal_functionality/test_uart.c) covering both instances, all parity/stop-bit combinations, and both priority IRQ handlers, runnable in CI without target hardware.

Acceptance Criteria

hal/mss/uart/hal_uart.c/.h implemented against this project's current hal/registers/component/uart.h/instance/uart.h
testing/mss/unit/hal_functionality/test_uart.c passes under ctest
Sanity-checked by deliberately breaking the baud-divisor formula and confirming the test suite catches it, then reverting

Functional Impact

None — self-contained addition alongside the already-landed GPIO/ESM drivers.

Regulatory Impact

None

QMS Impact

None

Risk Impact

No — existing risk coverage sufficient.

Relates to #4, relates to #75, relates to #77

### Description Adds `hal/mss/uart/hal_uart.c`/`.h` — the UART (SCI) driver: baud/parity/stop-bit init (TRM-derived divisor formula against the 200MHz VCLK), blocking transmit/receive with bounded ready-poll timeouts, IRQ source enable/disable/priority, and the four instance/priority-line raw handlers decoding `SCIFLR` to a weak, application-overridable `hal_uart_irq_handler()` hook. ### Use Case / Rationale As a firmware developer, I need a `hal_uart_*` API for blocking UART I/O and IRQ configuration, following the same driver pattern established by GPIO (#75) and ESM (#77). As a QMS reviewer, I need the baud-divisor formula's correctness (and its two representative divisor values) covered by an automated test, the same rigor already applied to GPIO/ESM. ### User Stories - As a developer, I want `hal_uart_init()` to compute `SCIBAUD` from a requested bit rate instead of hand-computing the TRM formula myself. - As a developer, I want `hal_uart_transmit()`/`hal_uart_receive()` to block with a bounded timeout rather than spin forever on a stuck/absent SCI. - As a QMS reviewer, I want a host-native Catch2 test suite (`testing/mss/unit/hal_functionality/test_uart.c`) covering both instances, all parity/stop-bit combinations, and both priority IRQ handlers, runnable in CI without target hardware. ### Acceptance Criteria - [x] `hal/mss/uart/hal_uart.c`/`.h` implemented against this project's current `hal/registers/component/uart.h`/`instance/uart.h` - [x] `testing/mss/unit/hal_functionality/test_uart.c` passes under `ctest` - [x] Sanity-checked by deliberately breaking the baud-divisor formula and confirming the test suite catches it, then reverting ### Functional Impact None — self-contained addition alongside the already-landed GPIO/ESM drivers. ### Regulatory Impact None ### QMS Impact None ### Risk Impact No — existing risk coverage sufficient. ### Related Issues / PRs Relates to #4, relates to #75, relates to #77