feat: MCAN driver implementation and host unit tests #97
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opendutchsolutions.public/hal_awr6843#97
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Description
Adds
hal/mss/mcan/hal_mcan.c/.h— the MCAN (Bosch M_CAN / CAN-FD controller) driver: MEM_INIT_DONE-then-reset-then-CCCR.INIT bring-up sequence (cross-checked against the mmwave SDK'sCANFD_open()), nominal bit-timing derivation (fixed 16-time-quantum, 75% sample point) from a requested classic-CAN bit rate, an "accept everything into Rx FIFO 0" global filter configuration, blocking transmit (dedicated Tx buffer 0, decodes PSR.LEC/BO into NACK/bus-error/bus-off status) and blocking receive (Rx FIFO 0, pop-and-acknowledge), and the two raw device handlers (MCAN_LVL0_IRQHandler/MCANB_LVL0_IRQHandler) decoding IR to a weak, application-overridablehal_mcan_irq_handler()hook. Both MCAN instances (MCANA/MCANB) supported.Deliberately minimal scope (documented in
hal_mcan.h's top-of-file comment): only classic CAN frames (no CAN-FD bit-rate switching/long-frame data phase), only standard 11-bit ID acceptance (no extended-ID filtering beyond the single global filter), one Rx FIFO and one set of dedicated Tx buffers (no Tx Event FIFO, no Rx FIFO 1, no dedicated Rx buffers), and no bus-off recovery automation.Use Case / Rationale
As a firmware developer, I need a
hal_mcan_*API for basic classic-CAN transmit/receive, following the same driver pattern established by GPIO, ESM, UART, I2C, SPI, ADCBUF, CBUFF, HWA, DMM, EPWM, and SOC — this is the final driver in the current driver-implementation batch.As a QMS reviewer, I need a host-native Catch2 test suite (
testing/mss/unit/hal_functionality/test_mcan.c) covering the bit-timing derivation math, the bring-up sequence, both transmit/receive paths and their error decoding, and both instances' IRQ handlers, runnable in CI without target hardware.Acceptance Criteria
hal/mss/mcan/hal_mcan.c/.himplemented against this project's currenthal/registers/component/mcan.h/instance/mcan.htesting/mss/unit/hal_functionality/test_mcan.cpasses underctestFunctional Impact
None — self-contained addition alongside the already-landed GPIO/ESM/UART/I2C/SPI/ADCBUF/CBUFF/HWA/DMM/EPWM/SOC drivers.
Regulatory Impact
None
QMS Impact
None
Risk Impact
No — existing risk coverage sufficient.
Related Issues / PRs
Relates to #4, relates to #75, relates to #77, relates to #79, relates to #81, relates to #83, relates to #85, relates to #87, relates to #89, relates to #91, relates to #93, relates to #95