feat: HWA driver implementation and host unit tests #89

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opened 2026-07-23 14:27:04 +00:00 by hoogv · 0 comments

hoogv commented

2026-07-23 14:27:04 +00:00

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Description

Adds hal/mss/hwa/hal_hwa.c/.h — the HWA (Hardware Accelerator) driver: reset/clock-gate bring-up (matching TI's own hwa.c reference sequence — ACCENABLE=0, pulse ACCRESET, ACCCLKEN=1, clear stale PARAMDONESTAT, zero all param-RAM entries), raw param-set-entry load (verbatim blob write, no structured field API — see rationale below), single-contiguous-range software trigger, and a poll-only completion check (hal_hwa_is_done()).

Deliberately minimal scope (documented in hal_hwa.h's top-of-file comment): no structured per-field param-set API (TI's CSL header is the only register-level source available — the TRM defers to an unavailable Radar HWA User's Guide — so several field semantics aren't confident enough to bake into a typed API), no multi-range chaining/looped execution, and no interrupt path (no MSS-reachable HWA completion IRQ exists — polling only).

Use Case / Rationale

As a firmware developer, I need a hal_hwa_* API for basic HWA bring-up and single-range param-set triggering, following the same driver pattern established by GPIO, ESM, UART, I2C, SPI, ADCBUF, and CBUFF.

As a QMS reviewer, I need a host-native Catch2 test suite (testing/mss/unit/hal_functionality/test_hwa.c) covering the reset/bring-up sequence, param-set load bounds checking, trigger range validation, and the done-poll/clear-on-completion logic, runnable in CI without target hardware.

Acceptance Criteria

hal/mss/hwa/hal_hwa.c/.h implemented against this project's current hal/registers/component/hwa.h/instance/hwa.h
testing/mss/unit/hal_functionality/test_hwa.c passes under ctest
Sanity-checked by deliberately breaking a register field/formula and confirming the test suite catches it, then reverting

Functional Impact

None — self-contained addition alongside the already-landed GPIO/ESM/UART/I2C/SPI/ADCBUF/CBUFF drivers.

Regulatory Impact

None

QMS Impact

None

Risk Impact

No — existing risk coverage sufficient.

Relates to #4, relates to #75, relates to #77, relates to #79, relates to #81, relates to #83, relates to #85, relates to #87

### Description Adds `hal/mss/hwa/hal_hwa.c`/`.h` — the HWA (Hardware Accelerator) driver: reset/clock-gate bring-up (matching TI's own `hwa.c` reference sequence — `ACCENABLE`=0, pulse `ACCRESET`, `ACCCLKEN`=1, clear stale `PARAMDONESTAT`, zero all param-RAM entries), raw param-set-entry load (verbatim blob write, no structured field API — see rationale below), single-contiguous-range software trigger, and a poll-only completion check (`hal_hwa_is_done()`). Deliberately minimal scope (documented in `hal_hwa.h`'s top-of-file comment): no structured per-field param-set API (TI's CSL header is the only register-level source available — the TRM defers to an unavailable Radar HWA User's Guide — so several field semantics aren't confident enough to bake into a typed API), no multi-range chaining/looped execution, and no interrupt path (no MSS-reachable HWA completion IRQ exists — polling only). ### Use Case / Rationale As a firmware developer, I need a `hal_hwa_*` API for basic HWA bring-up and single-range param-set triggering, following the same driver pattern established by GPIO, ESM, UART, I2C, SPI, ADCBUF, and CBUFF. As a QMS reviewer, I need a host-native Catch2 test suite (`testing/mss/unit/hal_functionality/test_hwa.c`) covering the reset/bring-up sequence, param-set load bounds checking, trigger range validation, and the done-poll/clear-on-completion logic, runnable in CI without target hardware. ### Acceptance Criteria - [x] `hal/mss/hwa/hal_hwa.c`/`.h` implemented against this project's current `hal/registers/component/hwa.h`/`instance/hwa.h` - [x] `testing/mss/unit/hal_functionality/test_hwa.c` passes under `ctest` - [x] Sanity-checked by deliberately breaking a register field/formula and confirming the test suite catches it, then reverting ### Functional Impact None — self-contained addition alongside the already-landed GPIO/ESM/UART/I2C/SPI/ADCBUF/CBUFF drivers. ### Regulatory Impact None ### QMS Impact None ### Risk Impact No — existing risk coverage sufficient. ### Related Issues / PRs Relates to #4, relates to #75, relates to #77, relates to #79, relates to #81, relates to #83, relates to #85, relates to #87

hoogv referenced this issue from a commit

2026-07-23 14:31:30 +00:00

feat(hwa): HWA driver implementation and host unit tests

hoogv referenced this issue from a pull request that will close it,

2026-07-23 14:31:59 +00:00

feat(hwa): HWA driver implementation and host unit tests #90

hoogv closed this issue

2026-07-23 15:02:49 +00:00

hoogv added this to the Development project

2026-07-23 15:03:30 +00:00

hoogv added this to the Revision V1.0 Launch milestone

2026-07-23 15:03:32 +00:00